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salla

ula_display

Jul 29th, 2019
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VHDL 1.21 KB | None | 0 0
  1. -- ULA com 4 bits de entrada e 5 bits de saida, opcode com 6 operacoes
  2. -- Autores: Joao Vitor e Marcos Meira
  3. -- Data 28/07/2017
  4.  
  5. library IEEE;
  6. use IEEE.STD_LOGIC_1164.ALL;
  7. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  8.  
  9. entity ula_display is
  10.     Port ( NUM1: in  STD_LOGIC_VECTOR (3 downto 0);    --
  11.            NUM2: in  STD_LOGIC_VECTOR (3 downto 0);    -- 4-bit number
  12.            op_code: in  STD_LOGIC_VECTOR (2 downto 0);
  13.              saida: out STD_LOGIC_VECTOR (4 downto 0));   -- 5 bit result
  14. end ula_display;
  15.  
  16. architecture behavioral of ula_display is
  17. sig_saida: std_LOGIC_VECTOR (4 downto 0);
  18. sig_decod0, sig_decod1: std_LOGIC_VECTOR (3 downto 0);
  19. begin
  20.  
  21.     process (op_code, NUM1, NUM2)
  22.     begin
  23.         case op_code is
  24.             when "000" => sig_saida <= ('0' & NUM1) + ('0' & NUM2);
  25.             when "001" => sig_saida <= ('0' & NUM1) - ('0' & NUM2);
  26.             when "010" => sig_saida <= ('0' & NUM1) and ('0' & NUM2);
  27.             when "011" => sig_saida <= ('0' & NUM1) or ('0' & NUM2);
  28.             when "100" => sig_saida <= ('0' & NUM1) xor ('0' & NUM2);
  29.             when "101" => sig_saida <= ('0' & NUM1) xnor ('0' & NUM2);
  30.             when others => sig_saida <= "00000";
  31.         end case;
  32.     end process;
  33.    
  34.     if sig_saida >= 10 then
  35.         sig_decod0 <= "0000";
  36.    
  37. end behavioral;
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