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  1. LIBRARY ieee;
  2. USE ieee.std_logic_1164.ALL;
  3. USE ieee.std_logic_unsigned.all;
  4. USE ieee.numeric_std.ALL;
  5. use IEEE.STD_LOGIC_TEXTIO.ALL;
  6. library std;
  7. use std.textio.all;
  8. library work;
  9. use WORK .fixed_pkg.all;
  10. use work.fixed_float_types.all;
  11.  
  12.  
  13.  
  14.  
  15. ENTITY LST1_tb_vhd IS
  16. END LST1_tb_vhd;
  17.  
  18. ARCHITECTURE behavior OF LST1_tb_vhd IS
  19.  
  20. -- Component Declaration for the Unit Under Test (UUT)
  21. COMPONENT LST_module
  22. PORT(
  23. clock_l : IN std_logic;
  24. reset_l : IN std_logic;
  25. read_en_l : IN std_logic;
  26. write_en_l : IN std_logic;
  27. outlar : IN std_logic_vector(15 downto 0);
  28. outlar2 : IN std_logic_vector(15 downto 0);
  29. LST_A : OUT std_logic_vector(15 downto 0);
  30. LST_B : OUT std_logic_vector(15 downto 0);
  31. LST1 : OUT ufixed (14 downto -11)
  32. );
  33. END COMPONENT;
  34.  
  35. --Inputs
  36. SIGNAL clock_l : std_logic := '0';
  37. SIGNAL reset_l : std_logic := '0';
  38. SIGNAL read_en_l : std_logic := '0';
  39. SIGNAL write_en_l : std_logic := '0';
  40. SIGNAL outlar : std_logic_vector(15 downto 0) := (others=>'0');
  41. SIGNAL outlar2 : std_logic_vector(15 downto 0) := (others=>'0');
  42.  
  43. --Outputs
  44. SIGNAL LST_A : std_logic_vector(15 downto 0);
  45. SIGNAL LST_B : std_logic_vector(15 downto 0);
  46. SIGNAL LST1 : ufixed (14 downto -11);
  47. constant PERIOD : time := 40 ns;
  48. BEGIN
  49.  
  50. -- Instantiate the Unit Under Test (UUT)^
  51. uut: LST_module PORT MAP(
  52. clock_l => clock_l,
  53. reset_l => reset_l,
  54. read_en_l => read_en_l,
  55. write_en_l => write_en_l,
  56. outlar => outlar,
  57. outlar2 => outlar2,
  58. LST_A => LST_A,
  59. LST_B => LST_B,
  60. LST1 => LST1
  61. );
  62.  
  63. tb : PROCESS
  64. BEGIN
  65.  
  66. -- PROCESS TO CONTROL THE CLOCK
  67.  
  68. clock_l <= '1';
  69. WAIT FOR PERIOD/2;
  70. clock_l <= '0';
  71. WAIT FOR PERIOD/2;
  72.  
  73. END PROCESS;
  74.  
  75. -- *** Test Bench - User Defined Section ***
  76.  
  77. tb2 : PROCESS
  78.  
  79. file myfile:text open read_mode is "C:UsershpDesktopLST1.txt";
  80. file myfile2:text open read_mode is "C:UsershpDesktopLST2.txt";
  81.  
  82. file myfile3:text open write_mode is "C:UsershpDesktopadd5.txt";
  83.  
  84. variable X: std_logic_vector(15 downto 0) := (others => '0');
  85. variable Y: std_logic_vector(15 downto 0) := (others => '0');
  86.  
  87. variable L: LINE;
  88.  
  89. BEGIN
  90.  
  91. WAIT FOR PERIOD ;
  92.  
  93. reset_l <= '0';
  94. read_en_l <= '0';
  95.  
  96. WAIT FOR PERIOD ;
  97.  
  98. reset_l <= '1';
  99. write_en_l <= '0';
  100. WAIT FOR PERIOD ;
  101. WAIT FOR PERIOD ;
  102. WAIT FOR PERIOD ;
  103.  
  104. while not ENDFILE(myfile) loop
  105. while not ENDFILE(myfile2) loop
  106. READLINE(myfile, L);
  107. READ(L,X);
  108. READLINE(myfile2, L);
  109. READ(L,Y);
  110.  
  111.  
  112. write_en_l <= '1';
  113. outlar <= X;
  114. outlar2 <= Y;
  115.  
  116. WAIT FOR PERIOD;
  117. write_en_l <= '0';
  118. WAIT FOR PERIOD;
  119. read_en_l <= '1';
  120. LST_A <= outlar;
  121. LST_B <= outlar2;
  122.  
  123. WAIT FOR PERIOD ;
  124.  
  125. write(L,LST1);
  126. writeline(myfile3,L);
  127. wait for PERIOD;
  128. wait for PERIOD;
  129. read_en_l <= '0';
  130. end loop;
  131. end loop;
  132. file_close(myfile);
  133. file_close(myfile2);
  134. END PROCESS;
  135. END behavior;
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