Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- USE ieee.std_logic_unsigned.all;
- USE ieee.numeric_std.ALL;
- use IEEE.STD_LOGIC_TEXTIO.ALL;
- library std;
- use std.textio.all;
- library work;
- use WORK .fixed_pkg.all;
- use work.fixed_float_types.all;
- ENTITY LST1_tb_vhd IS
- END LST1_tb_vhd;
- ARCHITECTURE behavior OF LST1_tb_vhd IS
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT LST_module
- PORT(
- clock_l : IN std_logic;
- reset_l : IN std_logic;
- read_en_l : IN std_logic;
- write_en_l : IN std_logic;
- outlar : IN std_logic_vector(15 downto 0);
- outlar2 : IN std_logic_vector(15 downto 0);
- LST_A : OUT std_logic_vector(15 downto 0);
- LST_B : OUT std_logic_vector(15 downto 0);
- LST1 : OUT ufixed (14 downto -11)
- );
- END COMPONENT;
- --Inputs
- SIGNAL clock_l : std_logic := '0';
- SIGNAL reset_l : std_logic := '0';
- SIGNAL read_en_l : std_logic := '0';
- SIGNAL write_en_l : std_logic := '0';
- SIGNAL outlar : std_logic_vector(15 downto 0) := (others=>'0');
- SIGNAL outlar2 : std_logic_vector(15 downto 0) := (others=>'0');
- --Outputs
- SIGNAL LST_A : std_logic_vector(15 downto 0);
- SIGNAL LST_B : std_logic_vector(15 downto 0);
- SIGNAL LST1 : ufixed (14 downto -11);
- constant PERIOD : time := 40 ns;
- BEGIN
- -- Instantiate the Unit Under Test (UUT)^
- uut: LST_module PORT MAP(
- clock_l => clock_l,
- reset_l => reset_l,
- read_en_l => read_en_l,
- write_en_l => write_en_l,
- outlar => outlar,
- outlar2 => outlar2,
- LST_A => LST_A,
- LST_B => LST_B,
- LST1 => LST1
- );
- tb : PROCESS
- BEGIN
- -- PROCESS TO CONTROL THE CLOCK
- clock_l <= '1';
- WAIT FOR PERIOD/2;
- clock_l <= '0';
- WAIT FOR PERIOD/2;
- END PROCESS;
- -- *** Test Bench - User Defined Section ***
- tb2 : PROCESS
- file myfile:text open read_mode is "C:UsershpDesktopLST1.txt";
- file myfile2:text open read_mode is "C:UsershpDesktopLST2.txt";
- file myfile3:text open write_mode is "C:UsershpDesktopadd5.txt";
- variable X: std_logic_vector(15 downto 0) := (others => '0');
- variable Y: std_logic_vector(15 downto 0) := (others => '0');
- variable L: LINE;
- BEGIN
- WAIT FOR PERIOD ;
- reset_l <= '0';
- read_en_l <= '0';
- WAIT FOR PERIOD ;
- reset_l <= '1';
- write_en_l <= '0';
- WAIT FOR PERIOD ;
- WAIT FOR PERIOD ;
- WAIT FOR PERIOD ;
- while not ENDFILE(myfile) loop
- while not ENDFILE(myfile2) loop
- READLINE(myfile, L);
- READ(L,X);
- READLINE(myfile2, L);
- READ(L,Y);
- write_en_l <= '1';
- outlar <= X;
- outlar2 <= Y;
- WAIT FOR PERIOD;
- write_en_l <= '0';
- WAIT FOR PERIOD;
- read_en_l <= '1';
- LST_A <= outlar;
- LST_B <= outlar2;
- WAIT FOR PERIOD ;
- write(L,LST1);
- writeline(myfile3,L);
- wait for PERIOD;
- wait for PERIOD;
- read_en_l <= '0';
- end loop;
- end loop;
- file_close(myfile);
- file_close(myfile2);
- END PROCESS;
- END behavior;
Add Comment
Please, Sign In to add comment