`define push        2'b00
`define pop         2'b01
`define push_prev   2'b10
`define idle        2'b11
`define IDLE        1'b0
`define WORK        1'b1

module queue(clk,reset,go,cmd,r_num,ready,w_en,r_en,full,almost_full,empty,almost_empty,error,w_num,addr);
    input clk,reset,go;
    input [17:0]cmd;
    input [15:0]r_num;

    output reg ready;
    output w_en,r_en;
    output full,almost_full,empty,almost_empty,error;
    output [15:0]w_num;
    output [4:0]addr;

    reg state, next_state;
    reg [15:0]pop_num, next_pop_num;
    reg [4:0]r_ad, next_r_ad, w_ad, next_w_ad, ad, next_ad;
    reg pop_check, next_pop_check, full_check, next_full_check;

    always@(posedge reset or posedge clk)begin
        if(reset == 1'b1)begin
            state <= `IDLE;
            ad <= 5'd0;
            r_ad <= 5'd0;
            w_ad <= 5'd0;
            pop_check <= 1'b0;
            full_check <= 1'b0;
        end
        else begin
            state <= next_state;
            pop_num <= next_pop_num;
            ad <= next_ad;
            r_ad <= next_r_ad;
            w_ad <= next_w_ad;
            pop_check <= next_pop_check;
            full_check <= next_full_check;
        end
    end

    always@(posedge clk)begin
        next_state = state;
        next_pop_num = pop_num;
        next_ad = ad;
        next_r_ad = r_ad;
        next_w_ad = w_ad;
        next_pop_check = pop_check;
        next_full_check = full_check;
        ready = (go == 1'b1 ? 1'b0 : 1'b1);
        case(state)
            `IDLE:begin
                next_state = (go == 1'b1 ? 1'b1 : 1'b0);
            end
            `WORK:begin
                next_state = (go == 1'b1 ? 1'b1 : 1'b0);
                if(cmd[17:16] == `push)begin
                    next_pop_num = pop_num;
                    next_ad = w_ad;
                    next_r_ad = r_ad;
                    next_w_ad = (w_ad == 5'd31 ? 5'd0 : w_ad+1);
                    next_pop_check = pop_check;
                    next_full_check = (w_ad == r_ad-1 ? 1'b1 : 1'b0);
                end
                else if(cmd[17:16] == `pop)begin
                    next_pop_num = cmd[15:0];
                    next_ad = r_ad;
                    next_r_ad = (r_ad == 5'd31 ? 5'd0 : r_ad+1);
                    next_w_ad = w_ad;
                    next_pop_check = 1'b1;
                    next_full_check = 1'b0;
                end
                else if(cmd[17:16] == `push_prev)begin
                    next_pop_num = pop_num;
                    next_ad = w_ad;
                    next_r_ad = r_ad;
                    next_w_ad = (w_ad == 5'd31 ? 5'd0 : w_ad+1);
                    next_pop_check = pop_check;
                    next_full_check = full_check;
                end
                else if(cmd[17:16] == `idle)begin

                end
            end
        endcase
        if(error == 1'b1 && state == `pop)begin
            r_ad = (r_ad == 5'd0 ? 5'd31 : r_ad-1);
        end
        else if(error == 1'b1 && (state == `push || state == `push_prev))begin
            w_ad = (w_ad == 5'd0 ? 5'd31 : w_ad-1);
        end
    end

    assign w_en = (state == `push || state == `push_prev) ? 1'b1 : 1'b0;
    assign r_en = (state == `pop) ? 1'b1 : 1'b0;
    assign full = (full_check == 1'b1) ? 1'b1 : 1'b0;
    assign almost_full = (w_ad == r_ad-1 || (w_ad == 5'd31 && r_ad == 5'd0)) ? 1'b1 : 1'b0;
    assign empty = (w_ad == r_ad && full_check == 1'b0) ? 1'b1 : 1'b0;
    assign almost_empty = (w_ad == r_ad+1 || (w_ad == 5'd0 && r_ad == 5'd31)) ? 1'b1 : 1'b0;
    assign error = ((full == 1'b1 && (state == `push || state == `push_prev)) ||  (pop_check == 1'b0 && state == `push_prev) ||
                    (empty == 1'b1 && state == `pop)) ? 1'b1 : 1'b0;
    assign w_num = (w_en == 1'b1) ? cmd[15:0] : 16'dX;
    assign addr = ad;

endmodule