localparam CLK10HZ_THRESH = 50_000_000 / 10;

reg clk10hz_en;
reg [$clog2(CLK10HZ_THRESH):0] clk10hz_counter;

initial clk10hz_en = 0;
initial clk10hz_counter = 0;

reg [3:0] state;
initial state = 0;

reg [7:0] led_state;
initial led_state = 0;

assign LED = led_state;

always @(posedge FPGA_CLK1_50) begin
   clk10hz_en <= 1'b0;
   if (clk10hz_counter == CLK10HZ_THRESH - 1)
   begin
      clk10hz_counter <= 0;
      clk10hz_en <= 1'b1;
   end
   else
      clk10hz_counter <= clk10hz_counter + 1'b1;
end

always @(posedge FPGA_CLK1_50) begin
   if (clk10hz_en)
      state = state + 1'b1;
end

integer ii;

generate
always @(*) begin
   for (ii = 0; ii < 8; ii = ii + 1)
      led_state[ii] = (state == ii || state == 15 - ii);
end
endgenerate

endmodule