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- when S1C =>
- Gate_MDR <= '1';
- LD_IR <= '1';
- LD_CC <= '1';
- LD_ADDR1MUX <= '1';
- MEM_EN <= '0';
- next_state <= S2;
- -------------------------------------
- ---- DECODE
- -------------------------------------
- when S2 =>
- OPCODE := INPUT_IR(15 downto 12);
- PC_OFFSET := INPUT_IR(8 downto 0);
- DR := INPUT_IR(11 downto 9); --destination register
- SR1 := INPUT_IR(8 downto 6); --source register 1
- SR2 := INPUT_IR(2 downto 0); --source register 2
- case OPCODE is
- when LOAD =>
- LD_IR <= '0';
- Gate_MDR <= '0';
- LD_PC <= '0';
- Gate_PC <= '0';
- LD_ADDR2MUX <= "01";
- LD_MM <= '1';
- Gate_MARMUX <= '1';
- LD_MAR <= '1';
- next_state <= S5;
- when S5 =>
- LD_MAR <= '1';
- MEM_EN <= '1';
- MEM_RW_EN <= '0';
- Gate_MARMUX <= '0';
- next_state <= S5A;
- when S5A =>
- LD_MAR <= '0';
- LD_MDR <= '0';
- Gate_MDR <= '1'; --put data on the bus
- LD_DR <= DR;
- LD_REG <= '1';
- next_state <= S5B;
- when S5B =>
- Gate_MDR <= '0';
- LD_REG <= '0';
- next_state <= S1;
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