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- .segment "HEADER"
- .include "nsf_wrap.s"
- .segment "CODE"
- ; VRC7[Y] <- A
- .macro vrc7write
- sty $9010
- jsr vrc7_delay2
- sta $9030
- jsr vrc7_delay
- .endmacro
- OCTAVE = 5
- VOLUME = 13
- DURATION = 120
- FREQ_LO = $00
- FREQ_HI = $01
- TRIGGER = $02 ; 00 -> nothing, 01 -> new note, 80 -> released
- LENGTH = $03
- READING = $04
- PATCHPOS = $05
- PATCHCOUNT = $06
- PATCHLOOP = $07
- PATCHREL = $08
- TIMER = $09
- var_Temp = $0A
- TEMP_X = $FF
- LOAD:
- INIT:
- tax
- lda vrc7freq_l, x
- sta FREQ_LO
- lda vrc7freq_h, x
- ora #(OCTAVE << 1)
- sta FREQ_HI
- lda #$00
- ldy #$30
- : vrc7write
- dey
- bpl :-
- ldy #$10
- lda FREQ_LO
- vrc7write
- ldy #$30
- lda #($0F - VOLUME)
- vrc7write
- ldx #$02
- : lda patchmacro, x
- sta PATCHCOUNT, x
- dex
- bpl :-
- jsr resetpatch
- rts
- PLAY:
- lda READING
- bne :+
- jmp @DoneLoading
- : lda LENGTH
- beq :+
- jmp @DoneLoading
- : lda PATCHPOS
- asl a
- asl a
- asl a
- ora #$07
- tax
- ldy #$07
- : lda patchdef, x
- vrc7write
- dex
- dey
- bpl :-
- lda PATCHPOS
- asl a
- tax
- inx
- inx
- inx
- lda patchmacro, x
- sta LENGTH
- lda TRIGGER
- bmi :+
- inx
- lda patchmacro, x
- bpl :+
- lda #$00
- jsr vrc7trigger
- lda #$01
- jsr vrc7trigger
- :
- inc PATCHPOS
- lda TRIGGER
- bpl @Looping
- @Releasing:
- lda PATCHPOS
- cmp PATCHCOUNT
- bcc @DoneLoading
- lda #$FF
- sta var_Temp
- lda PATCHLOOP
- cmp #$FF
- beq :+
- sta var_Temp
- lda PATCHREL
- cmp #$FF
- beq :+
- cmp var_Temp
- bcc :+
- sta var_Temp
- : lda var_Temp
- cmp #$FF
- bne :+
- lda #$00
- sta READING
- jmp @DoneLoading
- : sta PATCHPOS
- jmp @DoneLoading
- @Looping:
- lda PATCHREL
- sta var_Temp
- inc var_Temp
- bne :+
- lda PATCHCOUNT
- sta var_Temp
- : lda PATCHPOS
- cmp var_Temp
- bcc @DoneLoading
- lda PATCHLOOP
- cmp PATCHREL
- bcc :+
- lda #$00
- sta READING
- jmp @DoneLoading
- : lda PATCHLOOP
- sta PATCHPOS
- @DoneLoading:
- lda TRIGGER
- cmp #$01
- bne :+
- lda #$01
- jsr vrc7trigger
- lda #$00
- sta TRIGGER
- :
- dec LENGTH
- inc TIMER
- bne :+
- jsr resetpatch
- rts
- : lda #DURATION
- cmp TIMER
- bne :++
- lda PATCHREL
- cmp #$FF
- beq :+
- sta PATCHPOS
- asl a
- tax
- inx
- inx
- inx
- lda patchmacro, x
- sta LENGTH
- dec LENGTH
- : lda #$80
- sta TRIGGER
- lda #$01
- sta READING
- lda #$00
- jsr vrc7trigger
- : rts
- vrc7_delay:
- stx TEMP_X
- ldx #$08
- : dex
- bne :-
- ldx TEMP_X
- vrc7_delay2:
- rts
- resetpatch:
- lda #$01
- sta TRIGGER
- sta READING
- lda #$00
- sta PATCHPOS
- sta LENGTH
- rts
- vrc7trigger:
- beq :+
- lda #$10
- bpl :++ ; always
- : lda #$00
- : ora FREQ_HI
- ldy #$20
- vrc7write
- rts
- .define ft_vrc7_table 172, 183, 194, 205, 217, 230, 244, 258, 274, 290, 307, 326
- vrc7freq_l:
- .lobytes ft_vrc7_table
- vrc7freq_h:
- .hibytes ft_vrc7_table
- .macro VRC7PATCH tl,fb, ar0,dr0,sl0,rr0,kl0,mt0,am0,vb0,eg0,kr0,di0, ar1,dr1,sl1,rr1,kl1,mt1,am1,vb1,eg1,kr1,di1
- ; bit count 6 3 4 4 4 4 2 4 1 1 1 1 1 ...
- .byte ((am0 & $01) << 7) | ((vb0 & $01) << 6) | ((eg0 & $01) << 5) | ((kr0 & $01) << 4) | (mt0 & $0F)
- .byte ((am1 & $01) << 7) | ((vb1 & $01) << 6) | ((eg1 & $01) << 5) | ((kr1 & $01) << 4) | (mt1 & $0F)
- .byte ((kl0 & $03) << 6) | (tl & $3F)
- .byte ((kl1 & $03) << 6) | ((di0 & $01) << 4) | ((di1 & $01) << 3) | (fb & $07)
- .byte ((ar0 & $0F) << 4) | (dr0 & $0F)
- .byte ((ar1 & $0F) << 4) | (dr1 & $0F)
- .byte ((sl0 & $0F) << 4) | (rr0 & $0F)
- .byte ((sl1 & $0F) << 4) | (rr1 & $0F)
- .endmacro
- patchdef:
- ;TL,FB, AR,DR,SL,RR,KL,MT,AM,VB,EG,KR,DT, (same for carrier)
- VRC7PATCH 29,6, 15,0,0,0,0,1,0,0,0,0,0, 6,5,2,5,0,1,0,0,1,0,1
- VRC7PATCH 29,6, 15,0,0,0,0,0,0,0,0,0,0, 6,5,2,5,0,1,0,0,1,0,1
- VRC7PATCH 26,6, 15,0,0,0,0,0,0,0,0,0,0, 6,5,2,5,0,1,0,0,1,0,1
- VRC7PATCH 23,6, 15,0,0,0,0,0,0,0,0,0,0, 6,5,2,5,0,1,0,0,1,0,1
- VRC7PATCH 20,6, 15,0,0,0,0,0,0,0,0,0,0, 6,5,2,5,0,1,0,0,1,0,1
- VRC7PATCH 18,6, 15,0,0,0,0,0,0,0,0,0,0, 6,5,2,5,0,1,0,0,1,0,1
- VRC7PATCH 17,6, 15,0,0,0,0,0,0,1,0,0,0, 6,5,2,5,0,1,0,1,1,0,1
- VRC7PATCH 18,6, 15,0,0,0,0,0,0,1,0,0,0, 6,5,2,5,0,1,0,1,1,0,1
- VRC7PATCH 20,6, 15,0,0,0,0,0,0,1,0,0,0, 6,5,2,5,0,1,0,1,1,0,1
- VRC7PATCH 22,6, 15,0,0,0,0,0,0,1,0,0,0, 6,5,2,5,0,1,0,1,1,0,1
- VRC7PATCH 23,6, 15,0,0,0,0,0,0,1,0,0,0, 6,5,2,5,0,1,0,1,1,0,1
- patchmacro:
- .byte $0B ; count
- .byte $09 ; loop point (FF: hold)
- .byte $06 ; release point (FF: ignore)
- .byte $01, $80 ; length, flags
- .byte $02, $80 ; length, flags
- .byte $03, $00 ; length, flags
- .byte $03, $00 ; length, flags
- .byte $03, $00 ; length, flags
- .byte $03, $00 ; length, flags
- .byte $01, $00 ; length, flags
- .byte $01, $00 ; length, flags
- .byte $02, $00 ; length, flags
- .byte $02, $00 ; length, flags
- .byte $02, $00 ; length, flags
- ; flags:
- ; .7: retrigger (#$10 -> $2x, #$30 -> $2x)
- ; first tick always issues a trigger
- ; flag at 00 makes sense if loop point is also 00
- ; flag is ignored during note release (no ADSR resetting)
- ; .6 - .0: unused
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