module dmx (
    clock,
    tx

);

input clock;
output tx;

parameter s_break = 3'b000;
parameter s_mab = 3'b001;
parameter s_start_code = 3'b010
parameter s_tx_slots = 3'b011;
parameter s_idle = 3'b100

parameter clks_per_bit = 48
parameter break = 23
parameter mab = 3
parameter start_code = 3'b000
parameter slot = 3'b128
parameter num_slots = 9'b100000000

reg [2:0] r_sm_main = 0;
reg [7:0] r_clock_count = 0;
reg [9:0] r_slots_sent = 0;
reg [2:0] r_tx_bits_sent = 0;

always @(posedge clock)
    begin
        case (r_sm_main)
            s_idle :
                begin
                    tx <= 0;
                    r_clock_count <= 0:
                    r_sm_main <= s_break;
                end
            s_break :
                begin
                    if(r_clock_count < clocks_per_bit * break)
                    begin
                        tx <= 0;
                        r_sm_main <= s_break;
                        r_clock_count <= r_clock_count + 1;
                    end
                    else
                        r_sm_main <= s_mab;
                        r_clock_count <= 0;

                end
            s_mab :
                begin
                    if(r_clock_count < clocks_per_bit * mab)
                        begin
                            tx <= 1;
                            r_sm_main <= s_mab;
                            r_clock_count <= r_clock_count + 1;
                        end
                    else
                        r_clock_count <= 0;
                        r_sm_main <= s_tx_slots;
                end
            s_tx_slots :
                begin
                    if(r_clock_count < clocks_per_bit)
                    begin
                        if(r_slots_sent < num_slots)
                            begin
                                tx <= 0;
                                r_sm_main <= s_tx_slots;
                                r_clock_count <= r_clock_count + 1;
                            end


    end