import rv32i_types::*;

module cache #(
    parameter s_offset = 5,
    parameter s_index  = 3,
    parameter s_tag    = 32 - s_offset - s_index,
    parameter s_mask   = 2**s_offset,
    parameter s_line   = 8*s_mask,
    parameter num_sets = 2**s_index
)
(
	input clk,

	/* signals to CPU */
	output logic mem_resp,
	output rv32i_word mem_rdata,
	input logic mem_read,
	input logic mem_write,
	input logic [3:0] mem_byte_enable,
	input rv32i_word mem_address,
	input rv32i_word mem_wdata,

	/* signals from pmem */
	input logic [255:0] pmem_rdata,
	input logic pmem_resp,
	input logic pmem_address,
	input logic [255:0] pmem_wdata,
	input logic pmem_read,
	input logic pmem_write
);

/* datapath and control signals */
logic read_valid_0;
logic read_valid_1;
logic read_dirty_0;
logic read_dirty_1;
logic read_tag_0;
logic read_tag_1;
logic read_data_0;
logic read_data_1;
logic read_LRU;
logic load_valid_0;
logic load_valid_1;
logic load_dirty_0;
logic load_dirty_1;
logic load_tag_0;
logic load_tag_1;
logic load_data_0;
logic load_data_1;
logic load_LRU;
logic dirty_0_val;
logic dirty_1_val;
logic LRU_out;

/* bus adapter signals */
logic [255:0] mem_wdata256;
logic [255:0] mem_rdata256;
//logic [31:0] mem_wdata;
//logic [31:0] mem_rdata;
//logic [3:0] mem_byte_enable;
logic [31:0] mem_byte_enable256;
logic [31:0] address;

/* instantiating top-level cache blocks */
cache_datapath datapath
(
	.clk,
	.mem_address(mem_address),
	//.mem_wdata(mem_wdata),
	.mem_read(mem_read),
	//.mem_write(mem_write),
	.mem_byte_enable(mem_byte_enable),
	.pmem_rdata(pmem_rdata),
	.pmem_resp(pmem_resp),
	.mem_rdata(mem_rdata),
	.mem_resp(mem_resp),
	//.pmem_address(pmem_address),
	//.pmem_wdata(pmem_wdata),
	//.pmem_read(pmem_read),
	//.pmem_write(pmem_write),
	.read_valid_0(read_valid_0),
   .read_valid_1(read_valid_1),
   .read_dirty_0(read_dirty_0),
   .read_dirty_1(read_dirty_1),
   .read_tag_0(read_tag_0),
   .read_tag_1(read_tag_1),
   .read_data_0(read_data_0),
   .read_data_1(read_data_1),
   .read_LRU(read_LRU),
   .load_valid_0(load_valid_0),
   .load_valid_1(load_valid_1),
   .load_dirty_0(load_dirty_0),
   .load_dirty_1(load_dirty_1),
   .load_tag_0(load_tag_0),
   .load_tag_1(load_tag_1),
   .load_data_0(load_data_0),
   .load_data_1(load_data_1),
   .load_LRU(load_LRU),
   .dirty_0_val(dirty_0_val),
   .dirty_1_val(dirty_1_val),
	.mem_rdata256(mem_rdata256),
	.LRU_out(LRU_out)
);

cache_control control
(
	.mem_read(mem_read),
	.mem_write(mem_write),
	.mem_address(mem_address),
	.valid_0_out(valid_0_out),
	.valid_1_out(valid_1_out),
	.tag_0_out(tag_0_out),
	.tag_1_out(tag_1_out),
	.dirty_0_out(dirty_0_out),
	.dirty_1_out(dirty_1_out),
	.pmem_resp(pmem_resp),
	.LRU_out(LRU_out),
	.read_valid_0(read_valid_0),
	.read_valid_1(read_valid_1),
	.read_dirty_0(read_dirty_0),
	.read_dirty_1(read_dirty_1),
	.read_tag_0(read_tag_0),
	.read_tag_1(read_tag_1),
	.read_data_0(read_data_0),
	.read_data_1(read_data_1),
	.read_LRU(read_LRU),
	.load_valid_0(load_valid_0),
	.load_valid_1(load_valid_1),
	.load_dirty_0(load_dirty_0),
	.load_dirty_1(load_dirty_1),
	.load_tag_0(load_tag_0),
	.load_tag_1(load_tag_1),
	.load_data_0(load_data_0),
	.load_data_1(load_data_1),
	.load_LRU(load_LRU)
);

bus_adapter bus_adapter
(
    .mem_wdata256(mem_wdata256),
    .mem_rdata256(mem_rdata256),
    .mem_wdata(mem_wdata),
    .mem_rdata(mem_rdata),
    .mem_byte_enable(mem_byte_enable),
    .mem_byte_enable256(mem_byte_enable256),
    .address(address)
);

endmodule : cache