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Sep 17th, 2019
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4. entity FSM is
  5. port(
  6. Y: in std_logic_vector(7 downto 0);
  7. wr,clk,rst: in std_logic;
  8. add_wr,add_rd0,add_rd1,add_rd2: out integer range 0 to 3;
  9. ena: out std_logic;
  10. F: out std_logic_vector(2 downto 0);
  11. ready: out std_logic
  12.  
  13. );
  14. end FSM;
  15.  
  16. architecture arq of FSM is
  17. type states is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13);
  18. signal state, nxt_state: states;
  19.  
  20. component ALU_8 is
  21. port(
  22. A,B: in std_logic_vector(7 downto 0);
  23. F: in std_logic_vector(2 downto 0);
  24. Y: out std_logic_vector(7 downto 0);
  25. Over: out std_logic
  26. );
  27. end component;
  28.  
  29. component Reg is
  30. port(
  31. data_in: in std_logic_vector(7 downto 0);
  32. wr,clk: in std_logic;
  33. add_wr,add_rd0,add_rd1,add_rd2: in integer range 0 to 3;
  34. data_out0,data_out1,data_out2: out std_logic_vector(7 downto 0)
  35. );
  36. end component;
  37.  
  38. for alu1: ALU_8 use entity work.ALU_8;
  39.  
  40. for reg1: Reg use entity work.Reg;
  41. signal data_in: std_logic_vector(7 downto 0);
  42. signal add_wr,add_rd0,add_rd1,add_rd2: integer range 0 to 3;
  43. signal data_out0,data_out1,data_out2: std_logic_vector(7 downto 0)
  44.  
  45. begin
  46.  
  47. reg1: reg port map(data_in =>data_in, wr =>wr, clk => clk,
  48. add_wr =>add_wr, add_rd0 =>add_rd0, add_rd1 =>add_rd1, add_rd2 =>add_rd2,
  49. data_out0 =>data_out0, data_out1 =>data_out1, data_out2 =>data_out2);
  50.  
  51. process(clk,rst)
  52. begin
  53. if(clk'event and clk='1') then
  54. if (rst = '1') then
  55. state <= S0;
  56. else
  57. state <= nxt_state;
  58. end if;
  59. end if;
  60. end process;
  61.  
  62. process(state)
  63. begin
  64. if( state = S0 or state = S1 or state = S2 or state = S3 or
  65. state = S4 or state = S5 or state = S6 or state = S10 or
  66. state = S11 or state = S12 or state = S13 ) then
  67.  
  68. ready <= '0';
  69. else
  70. ready <= '1';
  71. end if;
  72. end process;
  73.  
  74. process(state)
  75. begin
  76. case state is
  77. when S0 =>
  78. ena <= '0';
  79. if( wr = '1') then
  80. nxt_state <= S1;
  81. add_wr = 1;
  82. else
  83. nxt_state <= S0;
  84. add_wr = 0;
  85. end if;
  86. when S1 =>
  87. ena <= '0';
  88. if( wr = '1') then
  89. nxt_state <= S2;
  90. add_wr = 2;
  91. else
  92. nxt_state <= S1;
  93. add_wr = 1;
  94. end if;
  95.  
  96. when S2 =>
  97. ena <= '0';
  98. if( wr = '1') then
  99. nxt_state <= S3;
  100. add_wr = 3;
  101. else
  102. nxt_state <= S2;
  103. add_wr = 2;
  104. end if;
  105.  
  106. when S3 =>
  107. if( wr = '1') then
  108. nxt_state <= S4;
  109. add_wr = 3;
  110. ena <= '1';
  111. add_rd0 = 0;
  112. add_rd1 = 1;
  113. -- Operación alu
  114. -- registro
  115. else
  116. nxt_state <= S3;
  117. add_wr = 3;
  118. ena <= '0';
  119. end if;
  120.  
  121. when S4 =>
  122. if( wr = '1') then
  123. nxt_state <= S4;
  124. add_wr = 3;
  125. ena <= '1';
  126. add_rd0 = 0;
  127. add_rd1 = 1;
  128. else
  129. nxt_state <= S3;
  130. add_wr = 3;
  131. ena <= '0';
  132. end if;
  133.  
  134.  
  135. end case;
  136. end process;
  137.  
  138. end arq;
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