display7

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity display7 is port
(
  clk, rst : in std_logic;
  an : out std_logic_vector(3 downto 0);
  sseg : out std_logic_vector (7 downto 0);
  in3, in2, in1, in0 : in std_logic_vector(3 downto 0)
);
end display7;

architecture arch of display7 is

  constant N : integer := 18;

  signal q_reg, q_next : unsigned (N-1 downto N-2);
  signal sel : std_logic_vector( 1 downto 0);
  signal mux_out : std_logic_vector (3 downto 0);

  begin

    process(clk, rst)
      begin
        if rst = '1' then
        q_reg <= (others => '0');
        elsif clk'event and clk = '1' then
        q_reg <= q_next;
        end if;
    end process;

    q_next <= q_reg + 1;
    sel <= std_logic_vector(q_reg(N-1 downto N-2));

    process(sel, in0, in1, in2, in3)
     begin
      case sel is
        when "00" => an <= "0001";
          mux_out <= in0;
        when "01" => an <= "0010";
          mux_out <= in1;
        when "10" => an <= "0100";
          mux_out <= in2;
        when others => an <= "1000";
          mux_out <= in3;
      end case;
    end process;

    with mux_out select
      sseg(7 downto 1) <=
        "1111110" when "0000", -- 0
        "0110000" when "0001", -- 1
        "1101101" when "0010", -- 2
        "1111001" when "0011", -- 3
        "0110011" when "0100", -- 4
        "1011011" when "0101", -- 5
        "1011111" when "0110", -- 6
        "1110000" when "0111", -- 7
        "1111111" when "1000", -- 8
        "1111011" when "1001", -- 9
        "0001110" when others; -- L
        sseg(0) <= '1';

end arch;