module swb2(SW, KEY, LEDR, HEX0, HEX1, HEX2, HEX3);
input [9:0] SW;
input [3:0] KEY;
output reg [9:0] LEDR;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output reg [6:0] HEX3;

always
begin
	if (KEY[0]==0)
		LEDR[9:0]=SW[9:5]+SW[4:0];
	else


	if (KEY[1]==0)
		if(SW[9:5] >= SW[4:0])
			LEDR[9:0]=SW[9:5]-SW[4:0];
		else
			LEDR[9:0]=SW[4:0]-SW[9:5];
	else


	if (KEY[2]==0)
		LEDR[9:0]=SW[9:5]*SW[4:0];
	else
		LEDR[9:0]=SW[9:0];
end

dec_to_hex y(LEDR % 10, HEX0);
dec_to_hex e((LEDR/10) % 10, HEX1);
dec_to_hex r(((LEDR/10)/10) % 10, HEX2);
always
	if (SW[9:5] < SW[4:0])
		HEX3 = 7'b0111111;
	else
		HEX3 = 7'b1111111;


endmodule

module dec_to_hex(digit, bits);
input [3:0] digit;
output reg [6:0] bits;

always
case (digit)
	0: bits = 7'b1000000;
	1: bits = 7'b1111001;
	2: bits = 7'b0100100;
	3: bits = 7'b0110000;
	4: bits = 7'b0011001;
	5: bits = 7'b0010010;
	6: bits = 7'b0000010;
	7: bits = 7'b1111000;
	8: bits = 7'b0000000;
	9: bits = 7'b0010000;
	default: bits = 7'b1111111;
endcase

endmodule