module freq(CLK, A1, A2);
   parameter COUNTER_LIMIT = 200_000_000;

   localparam WIDTH = $clog2(COUNTER_LIMIT) - 1;

   input wire CLK;
   input wire A1;
   output wire A2;

   reg [WIDTH:0] counter;
   reg [WIDTH:0] pulses;
   reg result;

   reg pulse_meta;
   reg pulse_current;
   reg pulse_prev;

   initial counter = COUNTER_LIMIT;
   initial pulses = 0;
   initial result = 0;
   initial pulse_meta = 0;
   initial pulse_current = 0;
   initial pulse_prev = 0;

   assign A2 = result;

   always @(posedge CLK) begin
     {pulse_prev, pulse_current, pulse_meta} <= {pulse_current, pulse_meta, A1};
     if (counter == 0)
       pulses <= 0;
     else if (pulse_current != pulse_prev)
       pulses <= pulses + 1;
   end

   always @(posedge CLK) begin
     if (counter == 0)
     begin
        counter <= COUNTER_LIMIT;
        result <= ^pulses;
     end
     else
        counter <= counter - 1;
   end
endmodule