system_stm32f4xx_c_olimex_E407.patch

--- system_stm32f4xx.orig.c 2012-09-17 13:20:00.000000000 +0200
+++ system_stm32f4xx.c  2012-09-28 00:43:32.000000000 +0200
@@ -2,12 +2,12 @@
   ******************************************************************************
   * @file    system_stm32f4xx.c
   * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    19-September-2011
+  * @version V1.0.1
+  * @date    28-September-2012
   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32F4xx devices,
   *          and is generated by the clock configuration tool
-  *          stm32f4xx_Clock_Configuration_V1.0.0.xls
+  *          stm32f4xx_Clock_Configuration_V1.0.1.xls
   *
   * 1.  This file provides two functions and one global variable to be called from
   *     user application:
@@ -34,7 +34,7 @@
   *    function will do nothing and HSI still used as system clock source. User can
   *    add some code to deal with this issue inside the SetSysClock() function.
   *
-  * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define
+  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
   *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
   *    through PLL, and you are using different crystal you have to adapt the HSE
   *    value to your own configuration.
@@ -56,9 +56,9 @@
   *-----------------------------------------------------------------------------
   *        APB2 Prescaler                         | 2
   *-----------------------------------------------------------------------------
-  *        HSE Frequency(Hz)                      | 8000000
+  *        HSE Frequency(Hz)                      | 12000000
   *-----------------------------------------------------------------------------
-  *        PLL_M                                  | 8
+  *        PLL_M                                  | 12
   *-----------------------------------------------------------------------------
   *        PLL_N                                  | 336
   *-----------------------------------------------------------------------------
@@ -66,15 +66,23 @@
   *-----------------------------------------------------------------------------
   *        PLL_Q                                  | 7
   *-----------------------------------------------------------------------------
-  *        PLLI2S_N                               | NA
+  *        PLLI2S_N                               | 271
   *-----------------------------------------------------------------------------
-  *        PLLI2S_R                               | NA
+  *        PLLI2S_R                               | 6
   *-----------------------------------------------------------------------------
-  *        I2S input clock                        | NA
+  *        I2S input clock(Hz)                    | 45000000
+  *                                               |
+  *        To achieve the following I2S config:   |
+  *         - Master clock output (MCKO): ON      |
+  *         - Frame wide                : 16bit   |
+  *         - Audio sampling freq (KHz) : 44,1    |
+  *         - Error %                   : 0,0000  |
+  *         - Prescaler Odd factor (ODD): 0       |
+  *         - Linear prescaler (DIV)    : 2       |
   *-----------------------------------------------------------------------------
-  *        VDD(V)                                 | 3.3
+  *        VDD(V)                                 | 3,3
   *-----------------------------------------------------------------------------
-  *        High Performance mode                  | Enabled
+  *        Main regulator output voltage          | Scale1 mode
   *-----------------------------------------------------------------------------
   *        Flash Latency(WS)                      | 5
   *-----------------------------------------------------------------------------
@@ -132,6 +140,7 @@
   * @{
   */

+/************************* Miscellaneous Configuration ************************/
 /*!< Uncomment the following line if you need to use external SRAM mounted
      on STM324xG_EVAL board as data memory  */
 /* #define DATA_IN_ExtSRAM */
@@ -141,10 +150,11 @@
 /* #define VECT_TAB_SRAM */
 #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
                                    This value must be a multiple of 0x200. */
+/******************************************************************************/

-
+/************************* PLL Parameters *************************************/
 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
-#define PLL_M      8
+#define PLL_M      12
 #define PLL_N      336

 /* SYSCLK = PLL_VCO / PLL_P */
@@ -153,6 +163,13 @@
 /* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
 #define PLL_Q      7

+/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N
+   I2SCLK = PLLI2S_VCO / PLLI2S_R */
+#define PLLI2S_N   271
+#define PLLI2S_R   6
+
+/******************************************************************************/
+
 /**
   * @}
   */
@@ -203,6 +220,10 @@
   */
 void SystemInit(void)
 {
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
   /* Reset the RCC clock configuration to the default reset state ------------*/
   /* Set HSION bit */
   RCC->CR |= (uint32_t)0x00000001;
@@ -358,9 +379,9 @@

   if (HSEStatus == (uint32_t)0x01)
   {
-    /* Enable high performance mode, System frequency up to 168 MHz */
+    /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-    PWR->CR |= PWR_CR_PMODE;
+    PWR->CR |= PWR_CR_VOS;

     /* HCLK = SYSCLK / 1*/
     RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
@@ -400,6 +421,23 @@
          configuration. User can add here some code to deal with this error */
   }

+
+/******************************************************************************/
+/*                          I2S clock configuration                           */
+/******************************************************************************/
+  /* PLLI2S clock used as I2S clock source */
+  RCC->CFGR &= ~RCC_CFGR_I2SSRC;
+
+  /* Configure PLLI2S */
+  RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);
+
+  /* Enable PLLI2S */
+  RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);
+
+  /* Wait till PLLI2S is ready */
+  while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)
+  {
+  }
 }

 /**
@@ -496,14 +534,14 @@

   /* Configure and enable Bank1_SRAM2 */
   FSMC_Bank1->BTCR[2]  = 0x00001015;
-  FSMC_Bank1->BTCR[3]  = 0x00010603;//0x00010400;
+  FSMC_Bank1->BTCR[3]  = 0x00010603;
   FSMC_Bank1E->BWTR[2] = 0x0fffffff;
-/*
+ /*
   Bank1_SRAM2 is configured as follow:

-  p.FSMC_AddressSetupTime = 3;//0;
+  p.FSMC_AddressSetupTime = 3;
   p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 6;//4;
+  p.FSMC_DataSetupTime = 6;
   p.FSMC_BusTurnAroundDuration = 1;
   p.FSMC_CLKDivision = 0;
   p.FSMC_DataLatency = 0;
@@ -524,8 +562,7 @@
   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-*/
-
+*/
 }
 #endif /* DATA_IN_ExtSRAM */