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-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
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-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
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-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- ***************************************************************************
-- Generated on "04/28/2018 18:28:30"

-- Vhdl Test Bench template for design  :  state_slat
--
-- Simulation tool : ModelSim-Altera (VHDL)
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY state_slat_vhd_tst IS
END state_slat_vhd_tst;
ARCHITECTURE state_slat_arch OF state_slat_vhd_tst IS
-- constants
constant clk_period: time := 20 ns;
-- signals
SIGNAL clk : STD_LOGIC;
SIGNAL izbaci_slatko : STD_LOGIC;
SIGNAL reset : STD_LOGIC := '1';
SIGNAL ubaci_5 : STD_LOGIC := '0';
SIGNAL ubaci_10 : STD_LOGIC := '0';
COMPONENT state_slat
    PORT (
    clk : IN STD_LOGIC;
    izbaci_slatko : OUT STD_LOGIC;
    reset : IN STD_LOGIC;
    ubaci_5 : IN STD_LOGIC;
    ubaci_10 : IN STD_LOGIC
    );
END COMPONENT;
BEGIN
    i1 : state_slat
    PORT MAP (
-- list connections between master ports and signals
    clk => clk,
    izbaci_slatko => izbaci_slatko,
    reset => reset,
    ubaci_5 => ubaci_5,
    ubaci_10 => ubaci_10
    );


clk_process : PROCESS
-- variable declarations
BEGIN
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
END PROCESS clk_process;


always : PROCESS
-- optional sensitivity list
-- (        )
-- variable declarations
BEGIN
        -- code executes for every event on sensitivity list
    reset <= '1';
    wait for 3*clk_period;
    reset <= '0';

    ubaci_5 <= '1';
    wait for clk_period;
    ubaci_5 <= '0';

    wait for 3*clk_period;

    ubaci_5 <= '1';
    wait for clk_period;
    ubaci_5 <= '0';



WAIT;
END PROCESS always;
END state_slat_arch;