tb_display7

library ieee;                                                         --biblioteca utilizada: ieee
use ieee.std_logic_1164.all;                                          --inclui todo o pacote padrão 1164
use ieee.numeric_std.all;

entity tb_display7 is
end entity;

architecture arch of tb_display7 is

component display7 is                                                   --inicio da declaração da entidade
  port( clk, rst : in std_logic;
    in3, in2, in1, in0 : std_logic_vector(3 downto 0);
    an : out std_logic_vector(3 downto 0);
    sseg : out std_logic_vector (7 downto 0)
);

end component;

    signal clk, rst :  std_logic;
    signal in3, in2, in1, in0 : std_logic_vector(3 downto 0);
    signal an :  std_logic_vector(3 downto 0);
    signal sseg :  std_logic_vector (7 downto 0);
begin
dut: display7 port map (clk, rst, in3, in2, in1, in0, an, sseg);

process
begin

clk <= '0';
wait for 10ns;
clk <= '1';
wait for 10ns;
end process;

process
begin

rst <= '1';
wait for 10ns;
rst <= '0';
wait;
end process;

process
begin

in3 <= "0000";
in2 <="0000";
in1 <= "0000";
in0 <="0000";


in3 <= "0100";
wait for 30ns;
in2 <="0111";
wait for 30ns;
in1 <= "0101";
wait for 30ns;
in0 <="1001";
wait;
end process;

end arch;