`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 30.08.2019 23:21:25
// Design Name:
// Module Name: user_pos_ctl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module user_pos_ctl(
    input wire clk,
    input wire rst,
    input wire [3:0] keys,       // {keyU,keyD,keyR,keyL}
    //input wire [17:0] st_obst_xy,       // st_obst_xy = {STAT_OBST_1_X,STAT_OBST_1_Y,STAT_OBST_2_X,STAT_OBST_2_Y,STAT_OBST_3_X,STAT_OBST_3_Y};

    output reg [11:0] xpos,
    output reg [11:0] ypos
);

reg [11:0] xpos_nxt, ypos_nxt;

always @(posedge clk) begin
    if (rst) begin
        xpos <= 0;
        ypos <= 0;
    end
    else begin
        xpos <= xpos_nxt;
        ypos <= ypos_nxt;
    end
end

always @* begin
    if (keys[3]) begin
        xpos_nxt = 300;
        ypos_nxt = 300;
    end
    else if (keys[2]) begin
        xpos_nxt = 400;
        ypos_nxt = 400;
    end
    else if (keys[1]) begin
        xpos_nxt = 500;
        ypos_nxt = 500;
    end
    else if (keys[0]) begin
        xpos_nxt = 100;
        ypos_nxt = 100;
    end
    else begin
        xpos_nxt = xpos;
        ypos_nxt = ypos;
    end
end
endmodule