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  1. ** licznik 74193 dekada rewersyjna **
  2. *
  3. * NI Multisim to SPICE Netlist Export
  4. * Generated by: oskar
  5. * Mon, Oct 21, 2019 21:07:33
  6. *
  7.  
  8. *## Multisim Component U4 ##*
  9. aU4 1 d_constsource_U4
  10. .model d_constsource_U4 d_constsource(state=1)
  11.  
  12.  
  13. *## Multisim Component X4 ##*
  14. * !!!BEGIN-INTERACT
  15. * : v_level ++++f2 ;
  16. * 0.0 VARIABLE r1Volt
  17. * 0.0 VARIABLE r1Cur
  18. *
  19. * :UPDATE_SETTINGS
  20. * 1 5 0 SET_SUBCOMP_PRP
  21. * 0 7 0 SET_SUBCOMP_PRP
  22. * 0 8 0 SET_SUBCOMP_PRP
  23. * 0 9 0 SET_SUBCOMP_PRP
  24. * 0 10 0 SET_SUBCOMP_PRP
  25. * 0 11 0 SET_SUBCOMP_PRP
  26. * 0 12 0 SET_SUBCOMP_PRP
  27. * 0 13 0 SET_SUBCOMP_PRP
  28. * 0 14 0 SET_SUBCOMP_PRP
  29. * 0.0 ==>_*r1Volt
  30. * 0.0 ==>_*r1Cur
  31. * ;
  32. *
  33. * :OUT_DATA
  34. * GET_INSTANCE Resistor ::R r1 i ==>_*r1Cur
  35. * 1.0e12 *r1Cur f.* ==>_*r1Volt
  36. * v_level *r1Volt f.<= if
  37. * 0 5 0 SET_SUBCOMP_PRP
  38. * 1 7 0 SET_SUBCOMP_PRP
  39. * 1 8 0 SET_SUBCOMP_PRP
  40. * 1 9 0 SET_SUBCOMP_PRP
  41. * 1 10 0 SET_SUBCOMP_PRP
  42. * 1 11 0 SET_SUBCOMP_PRP
  43. * 1 12 0 SET_SUBCOMP_PRP
  44. * 1 13 0 SET_SUBCOMP_PRP
  45. * 1 14 0 SET_SUBCOMP_PRP
  46. * else
  47. * 1 5 0 SET_SUBCOMP_PRP
  48. * 0 7 0 SET_SUBCOMP_PRP
  49. * 0 8 0 SET_SUBCOMP_PRP
  50. * 0 9 0 SET_SUBCOMP_PRP
  51. * 0 10 0 SET_SUBCOMP_PRP
  52. * 0 11 0 SET_SUBCOMP_PRP
  53. * 0 12 0 SET_SUBCOMP_PRP
  54. * 0 13 0 SET_SUBCOMP_PRP
  55. * 0 14 0 SET_SUBCOMP_PRP
  56. * endif
  57. * ;
  58. *
  59. * :BEGIN_PLOT
  60. * UPDATE_SETTINGS
  61. * ;
  62. * !!!END-INTERACT
  63. xX4 7 ProbeX4
  64. .subckt ProbeX4 1
  65. R1 1 0 1e12
  66. .ends
  67.  
  68. *## Multisim Component U5 ##*
  69. xU5 10 DIGITAL_CLOCK__DIGITAL_SOURCES__1 PARAMS: Frequency=10 Duty=50 Delay=0
  70.  
  71.  
  72. *## Multisim Component X3 ##*
  73. * !!!BEGIN-INTERACT
  74. * : v_level ++++f2 ;
  75. * 0.0 VARIABLE r1Volt
  76. * 0.0 VARIABLE r1Cur
  77. *
  78. * :UPDATE_SETTINGS
  79. * 1 5 0 SET_SUBCOMP_PRP
  80. * 0 7 0 SET_SUBCOMP_PRP
  81. * 0 8 0 SET_SUBCOMP_PRP
  82. * 0 9 0 SET_SUBCOMP_PRP
  83. * 0 10 0 SET_SUBCOMP_PRP
  84. * 0 11 0 SET_SUBCOMP_PRP
  85. * 0 12 0 SET_SUBCOMP_PRP
  86. * 0 13 0 SET_SUBCOMP_PRP
  87. * 0 14 0 SET_SUBCOMP_PRP
  88. * 0.0 ==>_*r1Volt
  89. * 0.0 ==>_*r1Cur
  90. * ;
  91. *
  92. * :OUT_DATA
  93. * GET_INSTANCE Resistor ::R r1 i ==>_*r1Cur
  94. * 1.0e12 *r1Cur f.* ==>_*r1Volt
  95. * v_level *r1Volt f.<= if
  96. * 0 5 0 SET_SUBCOMP_PRP
  97. * 1 7 0 SET_SUBCOMP_PRP
  98. * 1 8 0 SET_SUBCOMP_PRP
  99. * 1 9 0 SET_SUBCOMP_PRP
  100. * 1 10 0 SET_SUBCOMP_PRP
  101. * 1 11 0 SET_SUBCOMP_PRP
  102. * 1 12 0 SET_SUBCOMP_PRP
  103. * 1 13 0 SET_SUBCOMP_PRP
  104. * 1 14 0 SET_SUBCOMP_PRP
  105. * else
  106. * 1 5 0 SET_SUBCOMP_PRP
  107. * 0 7 0 SET_SUBCOMP_PRP
  108. * 0 8 0 SET_SUBCOMP_PRP
  109. * 0 9 0 SET_SUBCOMP_PRP
  110. * 0 10 0 SET_SUBCOMP_PRP
  111. * 0 11 0 SET_SUBCOMP_PRP
  112. * 0 12 0 SET_SUBCOMP_PRP
  113. * 0 13 0 SET_SUBCOMP_PRP
  114. * 0 14 0 SET_SUBCOMP_PRP
  115. * endif
  116. * ;
  117. *
  118. * :BEGIN_PLOT
  119. * UPDATE_SETTINGS
  120. * ;
  121. * !!!END-INTERACT
  122. xX3 6 ProbeX3
  123. .subckt ProbeX3 1
  124. R1 1 0 1e12
  125. .ends
  126.  
  127. *## Multisim Component X2 ##*
  128. * !!!BEGIN-INTERACT
  129. * : v_level ++++f2 ;
  130. * 0.0 VARIABLE r1Volt
  131. * 0.0 VARIABLE r1Cur
  132. *
  133. * :UPDATE_SETTINGS
  134. * 1 5 0 SET_SUBCOMP_PRP
  135. * 0 7 0 SET_SUBCOMP_PRP
  136. * 0 8 0 SET_SUBCOMP_PRP
  137. * 0 9 0 SET_SUBCOMP_PRP
  138. * 0 10 0 SET_SUBCOMP_PRP
  139. * 0 11 0 SET_SUBCOMP_PRP
  140. * 0 12 0 SET_SUBCOMP_PRP
  141. * 0 13 0 SET_SUBCOMP_PRP
  142. * 0 14 0 SET_SUBCOMP_PRP
  143. * 0.0 ==>_*r1Volt
  144. * 0.0 ==>_*r1Cur
  145. * ;
  146. *
  147. * :OUT_DATA
  148. * GET_INSTANCE Resistor ::R r1 i ==>_*r1Cur
  149. * 1.0e12 *r1Cur f.* ==>_*r1Volt
  150. * v_level *r1Volt f.<= if
  151. * 0 5 0 SET_SUBCOMP_PRP
  152. * 1 7 0 SET_SUBCOMP_PRP
  153. * 1 8 0 SET_SUBCOMP_PRP
  154. * 1 9 0 SET_SUBCOMP_PRP
  155. * 1 10 0 SET_SUBCOMP_PRP
  156. * 1 11 0 SET_SUBCOMP_PRP
  157. * 1 12 0 SET_SUBCOMP_PRP
  158. * 1 13 0 SET_SUBCOMP_PRP
  159. * 1 14 0 SET_SUBCOMP_PRP
  160. * else
  161. * 1 5 0 SET_SUBCOMP_PRP
  162. * 0 7 0 SET_SUBCOMP_PRP
  163. * 0 8 0 SET_SUBCOMP_PRP
  164. * 0 9 0 SET_SUBCOMP_PRP
  165. * 0 10 0 SET_SUBCOMP_PRP
  166. * 0 11 0 SET_SUBCOMP_PRP
  167. * 0 12 0 SET_SUBCOMP_PRP
  168. * 0 13 0 SET_SUBCOMP_PRP
  169. * 0 14 0 SET_SUBCOMP_PRP
  170. * endif
  171. * ;
  172. *
  173. * :BEGIN_PLOT
  174. * UPDATE_SETTINGS
  175. * ;
  176. * !!!END-INTERACT
  177. xX2 5 ProbeX2
  178. .subckt ProbeX2 1
  179. R1 1 0 1e12
  180. .ends
  181.  
  182. *## Multisim Component X1 ##*
  183. * !!!BEGIN-INTERACT
  184. * : v_level ++++f2 ;
  185. * 0.0 VARIABLE r1Volt
  186. * 0.0 VARIABLE r1Cur
  187. *
  188. * :UPDATE_SETTINGS
  189. * 1 5 0 SET_SUBCOMP_PRP
  190. * 0 7 0 SET_SUBCOMP_PRP
  191. * 0 8 0 SET_SUBCOMP_PRP
  192. * 0 9 0 SET_SUBCOMP_PRP
  193. * 0 10 0 SET_SUBCOMP_PRP
  194. * 0 11 0 SET_SUBCOMP_PRP
  195. * 0 12 0 SET_SUBCOMP_PRP
  196. * 0 13 0 SET_SUBCOMP_PRP
  197. * 0 14 0 SET_SUBCOMP_PRP
  198. * 0.0 ==>_*r1Volt
  199. * 0.0 ==>_*r1Cur
  200. * ;
  201. *
  202. * :OUT_DATA
  203. * GET_INSTANCE Resistor ::R r1 i ==>_*r1Cur
  204. * 1.0e12 *r1Cur f.* ==>_*r1Volt
  205. * v_level *r1Volt f.<= if
  206. * 0 5 0 SET_SUBCOMP_PRP
  207. * 1 7 0 SET_SUBCOMP_PRP
  208. * 1 8 0 SET_SUBCOMP_PRP
  209. * 1 9 0 SET_SUBCOMP_PRP
  210. * 1 10 0 SET_SUBCOMP_PRP
  211. * 1 11 0 SET_SUBCOMP_PRP
  212. * 1 12 0 SET_SUBCOMP_PRP
  213. * 1 13 0 SET_SUBCOMP_PRP
  214. * 1 14 0 SET_SUBCOMP_PRP
  215. * else
  216. * 1 5 0 SET_SUBCOMP_PRP
  217. * 0 7 0 SET_SUBCOMP_PRP
  218. * 0 8 0 SET_SUBCOMP_PRP
  219. * 0 9 0 SET_SUBCOMP_PRP
  220. * 0 10 0 SET_SUBCOMP_PRP
  221. * 0 11 0 SET_SUBCOMP_PRP
  222. * 0 12 0 SET_SUBCOMP_PRP
  223. * 0 13 0 SET_SUBCOMP_PRP
  224. * 0 14 0 SET_SUBCOMP_PRP
  225. * endif
  226. * ;
  227. *
  228. * :BEGIN_PLOT
  229. * UPDATE_SETTINGS
  230. * ;
  231. * !!!END-INTERACT
  232. xX1 4 ProbeX1
  233. .subckt ProbeX1 1
  234. R1 1 0 1e12
  235. .ends
  236.  
  237. *## Multisim Component U1 ##*
  238. aU1 [1
  239. + 10
  240. + U1_OPEN_CLR
  241. + 9
  242. + 1
  243. + 1
  244. + 1
  245. + 1]
  246. + [dU1.QA
  247. + dU1.QB
  248. + dU1.QC
  249. + dU1.QD
  250. + U1_OPEN_notCO
  251. + 9] 74193__74STD__1
  252.  
  253.  
  254.  
  255.  
  256.  
  257.  
  258. xU1.QA dU1.QA 4 VCC GND TTL_DRV__NON__1
  259.  
  260.  
  261. xU1.QB dU1.QB 5 VCC GND TTL_DRV__NON__1
  262.  
  263.  
  264. xU1.QC dU1.QC 6 VCC GND TTL_DRV__NON__1
  265.  
  266.  
  267. xU1.QD dU1.QD 7 VCC GND TTL_DRV__NON__1
  268.  
  269.  
  270.  
  271.  
  272.  
  273.  
  274.  
  275.  
  276. .subckt DIGITAL_CLOCK__DIGITAL_SOURCES__1 out PARAMS: Frequency=1k Duty=50 Delay=0
  277. A1 out DigClock
  278. .model DigClock d_clock (frequency={Frequency} duty={Duty/100} delay={Delay})
  279. .ends
  280.  
  281. .SUBCKT TTL_DRV__NON__1 1 2 3 4
  282. * TTL Driver Model 1 = D/A input, 2 = out 3= VCC 4 = VSS(GND)
  283. *#L1
  284. aDAC1in [1] [2] aDAC1
  285. .MODEL aDAC1 dac_bridge (out_low= 0 out_high = 5 out_undef = 2.5)
  286. *#L1
  287.  
  288. .ENDS
  289.  
  290. .MODEL 74193__74STD__1 d_chip ( behaviour= "
  291. +; 74193 SYNCHRONOUS BINARY UP/DOWN COUNTER WITH TWO CLOCKS
  292. +/inputs UP DOWN CLR ~LOAD A B C D
  293. +/outputs QA QB QC QD ~CO ~BO
  294. +/wires CLK DIR O1 O2 O3 O4
  295. +;
  296. +/module CLK_193
  297. +/inputs UP DOWN
  298. +/outputs CLK
  299. +/table 4
  300. +; U D CLK
  301. + L L L
  302. + H L L
  303. + L H L
  304. + H H H
  305. +/endmodule
  306. +/instance CLK_193 UP DOWN CLK
  307. +;
  308. +/module DIR_193
  309. +/inputs EN UP DOWN
  310. +/outputs DIR
  311. +;clock input_number edge{+|-} number_of_flags sync_entries async_entries
  312. +/clock EN X 1 1 3
  313. +;SYNC
  314. +;EN UP DOWN CF NF
  315. + X X X X F0
  316. +;ASYNC
  317. +;EN UP DOWN CF NF
  318. + X L H X H
  319. + X H L X L
  320. + X X X X F0
  321. +/table 1
  322. +;EN UP DOWN NF DIR
  323. + X X X X F0
  324. +/endmodule
  325. +/instance DIR_193 CLR UP DOWN DIR
  326. +;
  327. +/module CNTR_193
  328. +/inputs CLK DIR CLR ~LOAD A B C D
  329. +/outputs QA QB QC QD
  330. +;clock input_number edge{+|-} number_of_flags sync_entries async_entries
  331. +/clock CLK + 4 3 3
  332. +;SYNC
  333. +;CLK DIR CLR ~LOAD ABCD FFFF NF NF NF NF
  334. + X H L X XXXX XXXX F+0 F+1 F+2 F+3
  335. + X L L X XXXX XXXX F-0 F-1 F-2 F-3
  336. + X X X X XXXX XXXX F0 F1 F2 F3
  337. +;ASYNC
  338. +;CLK DIR CLR ~LOAD ABCD FFFF NF NF NF NF
  339. + X X H X XXXX XXXX L L L L
  340. + X X L L XXXX XXXX A B C D
  341. + X X X X XXXX XXXX F0 F1 F2 F3
  342. +/TABLE 1
  343. +;CLK DIR CLR ~LOAD DCBA FFFF QA QB QC QD
  344. + X X X X XXXX XXXX F0 F1 F2 F3
  345. +/endmodule
  346. +/instance CNTR_193 CLK DIR CLR ~LOAD A B C D O1 O2 O3 O4
  347. +;
  348. +/module CARRY
  349. +/inputs CLK DIR QA QB QC QD
  350. +/outputs ~CO
  351. +/table 2
  352. +; CLK DIR QA QB QC QD ~CO
  353. + L H H H H H L
  354. + X X X X X X H
  355. +/endmodule
  356. +/instance CARRY CLK DIR O1 O2 O3 O4 ~CO
  357. +;
  358. +/module BORROW
  359. +/inputs CLK DIR QA QB QC QD
  360. +/outputs ~BO
  361. +/table 2
  362. +; CLK DIR QA QB QC QD ~BO
  363. + L L L L L L L
  364. + X X X X X X H
  365. +/endmodule
  366. +/instance BORROW CLK DIR O1 O2 O3 O4 ~BO
  367. +;
  368. +/module MAPPING
  369. +/inputs ON
  370. +/outputs QN
  371. +/table 2
  372. +; ON QN
  373. + L L
  374. + H H
  375. +/endmodule
  376. +/instance MAPPING O1 QA
  377. +/instance MAPPING O2 QB
  378. +/instance MAPPING O3 QC
  379. +/instance MAPPING O4 QD
  380. +;
  381. +/delay 18
  382. +;input output Rise time Fall time
  383. + UP ~CO 26n 24n
  384. + DOWN ~BO 24n 24n
  385. + ~LOAD QA 40n 40n
  386. + ~LOAD QB 40n 40n
  387. + ~LOAD QC 40n 40n
  388. + ~LOAD QD 40n 40n
  389. + UP QA 38n 47n
  390. + UP QB 38n 47n
  391. + UP QC 38n 47n
  392. + UP QD 38n 47n
  393. + DOWN QA 38n 47n
  394. + DOWN QB 38n 47n
  395. + DOWN QC 38n 47n
  396. + DOWN QD 38n 47n
  397. + CLR QA X 35n
  398. + CLR QB X 35n
  399. + CLR QC X 35n
  400. + CLR QD X 35n
  401. +/constraint 24
  402. +; Name Event From Event To Min/Max Time
  403. + 'PULSE WIDTH' HL UP LH UP MIN 20n
  404. + 'PULSE WIDTH' LH UP HL UP MIN 20n
  405. + 'PULSE WIDTH' HL DOWN LH DOWN MIN 20n
  406. + 'PULSE WIDTH' LH DOWN HL DOWN MIN 20n
  407. + 'PULSE WIDTH' HL ~LOAD LH ~LOAD MIN 20n
  408. + 'PULSE WIDTH' LH CLR HL CLR MIN 20n
  409. + 'SETUP' LH A HL ~LOAD MIN 20n
  410. + 'SETUP' LH B HL ~LOAD MIN 20n
  411. + 'SETUP' LH C HL ~LOAD MIN 20n
  412. + 'SETUP' LH D HL ~LOAD MIN 20n
  413. + 'SETUP' HL A HL ~LOAD MIN 20n
  414. + 'SETUP' HL B HL ~LOAD MIN 20n
  415. + 'SETUP' HL C HL ~LOAD MIN 20n
  416. + 'SETUP' HL D HL ~LOAD MIN 20n
  417. + 'HOLD' LH UP LH ~LOAD MIN 3n
  418. + 'HOLD' LH DOWN LH ~LOAD MIN 3n
  419. + 'HOLD' HL ~LOAD HL A MIN 0n
  420. + 'HOLD' HL ~LOAD HL B MIN 0n
  421. + 'HOLD' HL ~LOAD HL C MIN 0n
  422. + 'HOLD' HL ~LOAD HL D MIN 0n
  423. + 'HOLD' HL ~LOAD LH A MIN 0n
  424. + 'HOLD' HL ~LOAD LH B MIN 0n
  425. + 'HOLD' HL ~LOAD LH C MIN 0n
  426. + 'HOLD' HL ~LOAD LH D MIN 0n
  427. +")
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