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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f4xx_it.c
  4.   * @brief   Interrupt Service Routines.
  5.   ******************************************************************************
  6.   *
  7.   * COPYRIGHT(c) 2017 STMicroelectronics
  8.   *
  9.   * Redistribution and use in source and binary forms, with or without modification,
  10.   * are permitted provided that the following conditions are met:
  11.   *   1. Redistributions of source code must retain the above copyright notice,
  12.   *      this list of conditions and the following disclaimer.
  13.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  14.   *      this list of conditions and the following disclaimer in the documentation
  15.   *      and/or other materials provided with the distribution.
  16.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  17.   *      may be used to endorse or promote products derived from this software
  18.   *      without specific prior written permission.
  19.   *
  20.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  23.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  24.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  26.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  27.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  28.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  29.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30.   *
  31.   ******************************************************************************
  32.   */
  33. /* Includes ------------------------------------------------------------------*/
  34. #include "stm32f4xx_hal.h"
  35. #include "stm32f4xx.h"
  36. #include "stm32f4xx_it.h"
  37.  
  38. /* USER CODE BEGIN 0 */
  39. //#include "PWM.h"
  40. #include "extern.h"
  41. #include "motor.h"
  42. #include "adc.h"
  43. int pwm = 0;
  44. unsigned int fade = 100;
  45. int current_phase = 0;
  46. int v_gnd = 0;
  47. int low_ADC=0;
  48. int flux = 0;
  49. int windup = 0;
  50. int b_zero_detected = 0;
  51. #define START_TIME 100
  52. #define THRESHOLD 10
  53. #define ZERO_DETECTED 100
  54. uint32_t x = DMA1_Stream0->CR;
  55.  
  56. /* USER CODE END 0 */
  57.  
  58. /* External variables --------------------------------------------------------*/
  59. extern DMA_HandleTypeDef hdma_adc1;
  60. extern TIM_HandleTypeDef htim3;
  61. extern TIM_HandleTypeDef htim4;
  62.  
  63. /******************************************************************************/
  64. /*            Cortex-M4 Processor Interruption and Exception Handlers         */
  65. /******************************************************************************/
  66.  
  67. /**
  68. * @brief This function handles Non maskable interrupt.
  69. */
  70. void NMI_Handler(void)
  71. {
  72.   /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
  73.  
  74.   /* USER CODE END NonMaskableInt_IRQn 0 */
  75.   /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  76.  
  77.   /* USER CODE END NonMaskableInt_IRQn 1 */
  78. }
  79.  
  80. /**
  81. * @brief This function handles Hard fault interrupt.
  82. */
  83. void HardFault_Handler(void)
  84. {
  85.   /* USER CODE BEGIN HardFault_IRQn 0 */
  86.  
  87.   /* USER CODE END HardFault_IRQn 0 */
  88.   while (1)
  89.   {
  90.   }
  91.   /* USER CODE BEGIN HardFault_IRQn 1 */
  92.  
  93.   /* USER CODE END HardFault_IRQn 1 */
  94. }
  95.  
  96. /**
  97. * @brief This function handles Memory management fault.
  98. */
  99. void MemManage_Handler(void)
  100. {
  101.   /* USER CODE BEGIN MemoryManagement_IRQn 0 */
  102.  
  103.   /* USER CODE END MemoryManagement_IRQn 0 */
  104.   while (1)
  105.   {
  106.   }
  107.   /* USER CODE BEGIN MemoryManagement_IRQn 1 */
  108.  
  109.   /* USER CODE END MemoryManagement_IRQn 1 */
  110. }
  111.  
  112. /**
  113. * @brief This function handles Pre-fetch fault, memory access fault.
  114. */
  115. void BusFault_Handler(void)
  116. {
  117.   /* USER CODE BEGIN BusFault_IRQn 0 */
  118.  
  119.   /* USER CODE END BusFault_IRQn 0 */
  120.   while (1)
  121.   {
  122.   }
  123.   /* USER CODE BEGIN BusFault_IRQn 1 */
  124.  
  125.   /* USER CODE END BusFault_IRQn 1 */
  126. }
  127.  
  128. /**
  129. * @brief This function handles Undefined instruction or illegal state.
  130. */
  131. void UsageFault_Handler(void)
  132. {
  133.   /* USER CODE BEGIN UsageFault_IRQn 0 */
  134.  
  135.   /* USER CODE END UsageFault_IRQn 0 */
  136.   while (1)
  137.   {
  138.   }
  139.   /* USER CODE BEGIN UsageFault_IRQn 1 */
  140.  
  141.   /* USER CODE END UsageFault_IRQn 1 */
  142. }
  143.  
  144. /**
  145. * @brief This function handles System service call via SWI instruction.
  146. */
  147. void SVC_Handler(void)
  148. {
  149.   /* USER CODE BEGIN SVCall_IRQn 0 */
  150.  
  151.   /* USER CODE END SVCall_IRQn 0 */
  152.   /* USER CODE BEGIN SVCall_IRQn 1 */
  153.  
  154.   /* USER CODE END SVCall_IRQn 1 */
  155. }
  156.  
  157. /**
  158. * @brief This function handles Debug monitor.
  159. */
  160. void DebugMon_Handler(void)
  161. {
  162.   /* USER CODE BEGIN DebugMonitor_IRQn 0 */
  163.  
  164.   /* USER CODE END DebugMonitor_IRQn 0 */
  165.   /* USER CODE BEGIN DebugMonitor_IRQn 1 */
  166.  
  167.   /* USER CODE END DebugMonitor_IRQn 1 */
  168. }
  169.  
  170. /**
  171. * @brief This function handles Pendable request for system service.
  172. */
  173. void PendSV_Handler(void)
  174. {
  175.   /* USER CODE BEGIN PendSV_IRQn 0 */
  176.  
  177.   /* USER CODE END PendSV_IRQn 0 */
  178.   /* USER CODE BEGIN PendSV_IRQn 1 */
  179.  
  180.   /* USER CODE END PendSV_IRQn 1 */
  181. }
  182.  
  183. /**
  184. * @brief This function handles System tick timer.
  185. */
  186. void SysTick_Handler(void)
  187. {
  188.   /* USER CODE BEGIN SysTick_IRQn 0 */
  189.  
  190.   /* USER CODE END SysTick_IRQn 0 */
  191.   HAL_IncTick();
  192.   HAL_SYSTICK_IRQHandler();
  193.   /* USER CODE BEGIN SysTick_IRQn 1 */
  194.  
  195.   /* USER CODE END SysTick_IRQn 1 */
  196. }
  197.  
  198. /******************************************************************************/
  199. /* STM32F4xx Peripheral Interrupt Handlers                                    */
  200. /* Add here the Interrupt Handlers for the used peripherals.                  */
  201. /* For the available peripheral interrupt handler names,                      */
  202. /* please refer to the startup file (startup_stm32f4xx.s).                    */
  203. /******************************************************************************/
  204.  
  205. /**
  206. * @brief This function handles TIM3 global interrupt.
  207. */
  208. void TIM3_IRQHandler(void)
  209. {
  210.   /* USER CODE BEGIN TIM3_IRQn 0 */
  211. //  if ((pwm+fade > TIM3->ARR ) | (pwm+fade < 1)){
  212. //    fade = -fade;
  213. //  }
  214. //  pwm = pwm + fade;
  215. //  __HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_1, pwm);
  216.   /* USER CODE END TIM3_IRQn 0 */
  217.   HAL_TIM_IRQHandler(&htim3);
  218.   /* USER CODE BEGIN TIM3_IRQn 1 */
  219.  
  220.   /* USER CODE END TIM3_IRQn 1 */
  221. }
  222.  
  223. /**
  224. * @brief This function handles TIM4 global interrupt.
  225. */
  226. void TIM4_IRQHandler(void)
  227. {
  228.   /* USER CODE BEGIN TIM4_IRQn 0 */
  229.  
  230.   /* USER CODE END TIM4_IRQn 0 */
  231.   HAL_TIM_IRQHandler(&htim4);
  232.   /* USER CODE BEGIN TIM4_IRQn 1 */
  233.  
  234.   /* USER CODE END TIM4_IRQn 1 */
  235. }
  236.  
  237. /**
  238. * @brief This function handles DMA2 stream0 global interrupt.
  239. */
  240. void DMA2_Stream0_IRQHandler(void)
  241. {
  242.   /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
  243.  
  244.   /* USER CODE END DMA2_Stream0_IRQn 0 */
  245.   HAL_DMA_IRQHandler(&hdma_adc1);
  246.   /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
  247.  
  248.   /* USER CODE END DMA2_Stream0_IRQn 1 */
  249. }
  250.  
  251. /* USER CODE BEGIN 1 */
  252.  
  253. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  254. {
  255.   HAL_ADC_Stop_DMA(&hadc1);
  256.   if(htim == &htim4){
  257.     GPIOC->ODR |= phase_mask[current_phase];
  258.     HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCValue,10);
  259.     if(windup>=START_TIME){
  260.       switch(current_phase)
  261.       {
  262.         case 0:
  263.           //v_gnd = (ADCValue[1] + ADCValue [2])/2;
  264.           if(ADCValue[0]-low_ADC<ZERO_DETECTED){
  265.             b_zero_detected=1;
  266.       HAL_GPIO_TogglePin(GPIOB, LED_Pin);
  267.           }
  268.           if(b_zero_detected){
  269.             flux+=ADCValue[0];
  270.           }
  271.           if(flux >= THRESHOLD){
  272.             current_phase = 1;
  273.             flux = 0;
  274.             b_zero_detected=0;
  275.           }
  276.           break;
  277.  
  278.         case 1:
  279.           //v_gnd = (ADCValue[0] + ADCValue [2])/2;
  280.           if(ADCValue[1]-low_ADC<ZERO_DETECTED){
  281.             b_zero_detected=1;
  282.           }
  283.           if(b_zero_detected){
  284.             flux+=ADCValue[1];
  285.           }
  286.           if(flux >= THRESHOLD){
  287.             current_phase = 2;
  288.             flux = 0;
  289.             b_zero_detected=0;
  290.           }
  291.           break;
  292.         case 2:
  293.           //v_gnd = (ADCValue[0] + ADCValue [1])/2;
  294.           if(ADCValue[2]-low_ADC<ZERO_DETECTED){
  295.             b_zero_detected=1;
  296.           }
  297.           if(b_zero_detected){
  298.             flux+=ADCValue[2];
  299.           }
  300.           if(flux >= THRESHOLD){
  301.             current_phase = 3;
  302.             flux = 0;
  303.             b_zero_detected=0;
  304.           }
  305.           break;
  306.         case 3:
  307.           //v_gnd = (ADCValue[1] + ADCValue [2])/2;
  308.           if(ADCValue[0]-low_ADC<ZERO_DETECTED){
  309.             b_zero_detected=1;
  310.           }
  311.           if(b_zero_detected){
  312.             flux+=ADCValue[0];
  313.           }
  314.           if(flux >= THRESHOLD){
  315.             current_phase = 4;
  316.             flux = 0;
  317.             b_zero_detected=0;
  318.           }
  319.           break;
  320.         case 4:
  321.           //v_gnd = (ADCValue[0] + ADCValue [2])/2;
  322.           if(ADCValue[1]-low_ADC<ZERO_DETECTED){
  323.             b_zero_detected=1;
  324.           }
  325.           if(b_zero_detected){
  326.             flux+=ADCValue[1];
  327.           }
  328.           if(flux >= THRESHOLD){
  329.             current_phase = 5;
  330.             flux = 0;
  331.             b_zero_detected=0;
  332.           }
  333.           break;
  334.         case 5:
  335.           //v_gnd = (ADCValue[0] + ADCValue [1])/2;
  336.           if(ADCValue[2]-low_ADC<ZERO_DETECTED){
  337.             b_zero_detected=1;
  338.           }
  339.           if(b_zero_detected){
  340.             flux+=ADCValue[2];
  341.           }
  342.           if(flux >= THRESHOLD){
  343.             current_phase = 0;
  344.             flux = 0;
  345.           }
  346.           break;
  347.         default:
  348.           break;
  349.  
  350.       }
  351.     }
  352.   }
  353.  
  354.   if (htim == &htim3){
  355.     if (windup < START_TIME){
  356.     current_phase++;
  357.     if (current_phase > 5){current_phase = 0;}
  358.     windup++;
  359.     }
  360.   }
  361. HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCValue,10);
  362. }
  363.  
  364. void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
  365. {
  366. HAL_ADC_Stop_DMA(&hadc1);
  367.   //if(htim == &htim4){
  368.     GPIOC->ODR &= 0x00;
  369.     {
  370. //    HAL_ADC_Start_DMA(&hadc1, (uint32_t1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
  371.       switch(current_phase)
  372.       {
  373.         case 0:
  374.           low_ADC=ADCValue[0];
  375.           break;
  376.         case 1:
  377.           low_ADC=ADCValue[1];
  378.           break;
  379.         case 2:
  380.           low_ADC=ADCValue[2];
  381.           break;
  382.         case 3:
  383.           low_ADC=ADCValue[0];
  384.           break;
  385.         case 4:
  386.           low_ADC=ADCValue[1];
  387.           break;
  388.         case 5:
  389.           low_ADC=ADCValue[2];
  390.           break;
  391.         default:
  392.           break;
  393.  
  394.       }
  395.     }
  396. HAL_ADC_Start_DMA(&hadc1, (*)ADCValue,10);
  397. }
  398.  
  399. /* USER CODE END 1 */
  400. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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