BinaryToDecimal

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY BinaryToDecimal IS
 PORT (SW: IN UNSIGNED(3 DOWNTO 0);
       HEX0, HEX1; OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END BinaryToDecimal;
ARCHITECTURE Behavior of BinaryToDecimal IS

--COMPONENTS
COMPONENT comparator
PORT (V: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        Z: OUT STD_LOGIC);
END COMPONENT;
COMPONENT mux_2to1
PORT(X,Y,S: IN STD_LOGIC;
    M: OUT STD_LOGIC);
END COMPONENT;
COMPONENT circuitB
PORT (INPUT: IN STD_LOGIC;
         HEX1: OUT STD_LOGIC_VECTOR(0 TO 6));
END COMPONENT;
COMPONENT SevenSegmentDecoder
PORT (SW : IN STD_LOGIC_VECTOR(0 TO 2);
        HEX0: OUT STD_LOGIC_VECTOR(0 TO 6));
END COMPONENT;
--add here circuitA component

--INTERNAL SIGNALS
SIGNAL out_comp: STD_LOGIC;
SIGNAL out_A: STD_LOGIC(2 DOWNTO 0);
SIGNAL out_mux: STD_LOGIC(3 DOWNTO 0);
SIGNAL in_mux: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL in_comp: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN
--giving the inputs to multiplexers, circuitA, comparator
in_mux<=STD_LOGIC_VECTOR(SW);
in_comp <= STD_LOGIC_VECTOR(SW);
COMP: comparator PORT MAP(x_comp,out_comp);
CA: circuitA PORT MAP(SW(2 DOWNTO 0),uscitaA );
MUX1:mux_2to1 PORT MAP(x_mux(3), '0', out_comp, out_mux(3));
MUX2:mux_2to1 PORT MAP(x_mux(2), out_A(2), out_comp, out_mux(2));
MUX3:mux_2to1 PORT MAP(x_mux(1), out_A(1), out_comp, out_mux(1));
MUX4:mux_2to1 PORT MAP(x_mux(0), out_A(0), out_comp, out_mux(0));
CB: circuitB PORT MAP(out_comp,HEX1(0 TO 6));
DEC: decoder PORT MAP(out_mux(3 DOWNTO 0), HEX0(0 TO 6));
END structure;