wire clk_pll_raw,clk_pll,Q1A,Q2A,Q1B,Q2B;
          wire CLK_A,CLK_A_raw,CLK_B,CLK_B_raw;

          IBUFDS IBUFDS_CLKA(.O(CLK_A_raw),.I(CLK_A_P),.IB(CLK_A_N));
          BUFG CLKA(.O(CLK_A),.I(CLK_A_raw));

          IBUFDS IBUFDS_CLKB(.O(CLK_B_raw),.I(CLK_B_P),.IB(CLK_B_N));
          BUFG CLKB(.O(CLK_B),.I(CLK_B_raw));


          IBUFDS IBUFDS_clkpll(.O(clk_pll_raw),.I(CLK_P),.IB(CLK_N));
          BUFG BUFG_clkpll(.I(clk_pll_raw),.O(clk_pll));
          IBUFDS IBUFDS_Q1A (.O(Q1A), .I(Q1A_P), .IB(Q1A_N));
          IBUFDS IBUFDS_Q2A (.O(Q2A), .I(Q2A_P), .IB(Q2A_N));
          IBUFDS IBUFDS_Q1B (.O(Q1B), .I(Q1B_P), .IB(Q1B_N));
          IBUFDS IBUFDS_Q2B (.O(Q2B), .I(Q2B_P), .IB(Q2B_N));


          //
          reg reset_MEM = 1'b1;
          integer rst_counter_mem =0;
          always @ ( posedge clk )
          begin
             if (rst_counter_mem < 100000)
             begin
                 reset_MEM <=  1'b1;
                 rst_counter_mem = rst_counter_mem +1;
             end
             else  reset_MEM <= 1'b0;
          end







          //Definitions of MEM1 inputs
          wire clk_mem1,clk_obs1;
        //   assign clk_obs1 = Q1A;  //Here
        //   assign clk_mem1 = clk_pll&(~reset_MEM);
          assign clk_obs1 = clk_5000;  //Here
          assign clk_mem1 = CLK_A&(~reset_MEM);



          reg [31:0] counter1=32'b0;
          always @(posedge clk_mem1)   //Here
          begin
          counter1 <= counter1+1'b1;
          end


          reg [31:0] write_loc1=32'b0;
          reg pre_state1 = 1'b0;
          reg flipped1= 1'b0;

          always @(negedge clk_mem1)   //Here
          begin

          // initialising the clock with the original state
          if(flipped1 == 0)
          begin
           pre_state1 <= clk_obs1;
           flipped1<=1'b1;
          end //if

          else if (pre_state1 == ~clk_obs1)//Checking if the state was changed
          begin
           pre_state1<=clk_obs1;

          //Writing to MEM
          if(write_loc1 < MEM_DEPTH)
          begin
              MEM1[write_loc1] <= 32'd12345678;//counter1;
              write_loc1<= write_loc1+1'b1;
          end //if

          end //elseif
          end //always