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-- Company:
-- Engineer:
--
-- Create Date:    20:24:27 03/25/2019
-- Design Name:
-- Module Name:    rs32 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rs32 is
    Port ( RXD_i : in  STD_LOGIC;
           clk_i : in  STD_LOGIC;
           data_o : out  STD_LOGIC_VECTOR (7 downto 0));
end rs32;

architecture Behavioral of rs32 is
	signal receiving: std_logic := '0';
	signal data_cnt: integer := 0;
	signal time_cnt: integer := 0;
begin
	process(clk_i, RXD_i, data_o):
		if rising_edge(clk_i):
			if receiving = '0' and RXD_i = '0' then
				receiving <= '1';
				data_cnt <= 1;
			end if;

			if receiving = '1' then
				time_cnt <= time_cnt + 1;
				if time_cnt >= 5210 then
					time_cnt <= 0;
					if data_cnt < 10 then
						digit_o(data_cnt - 1) <= RXD_i;
						data_cnt <= data_cnt +1;
					end if;
				end if;
			end if;

			if data_cnt = 10 then
				data_cnt <= 0;
				receiving <= '0';
		end if;
	end process;

end Behavioral;