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- list p=18F1220 ; Set processor type
- radix hex ; Sets the default radix for data exp.
- config WDT=OFF, LVP=OFF, OSC = INTIO2 ; Disable Watchdog timer, Low V. Prog, and RA6 as a clock
- #define ADCON1 0xFC1
- #define PORTB 0xF81
- #define TRISB 0xF93
- #define WREG 0xFE8
- LAST equ 0x80
- CURR_A equ 0x81
- RESULT equ 0x82
- org 0x00
- ; this is just a bunch of dumb setup
- CLRF PORTB
- CLRF TRISB
- ; what does this do? nobody knows
- MOVLW 0x7F
- MOVWF ADCON1
- ; in binary this is 0001 1111
- ; means that pins RB0-RB5 are inputs, rest are outputs
- ; why 5 pins? it works
- MOVLW 0x1F
- MOVWF TRISB
- CLRF LAST
- CLRF CURR_A
- Loop:
- ; Put the value from PORTB into WREG
- MOVF PORTB, 0
- ; Check and see if it's different from the last value
- XORWF LAST, 0
- ; If it is different, branch over to CalcSum
- BNZ CalcSum
- ; Redo the loop
- GOTO Loop
- CalcSum:
- ; Grab the value of A and put it into CURR_A
- MOVF PORTB, 0
- ANDLW 0x3 ; W = A
- MOVWF CURR_A
- ; Grab the value of B and put it in WREG
- ; (we have to shift it to the right and AND it
- ; to ensure we have ONLY the bits we want)
- MOVF PORTB, 0
- RRNCF WREG
- RRNCF WREG
- ANDLW 0x3 ; W = B
- ; Add the value in WREG (aka B) with the value
- ; in CURR_A (aka A), and put the result in WREG
- ADDWF CURR_A, 0
- ; Put the sum of A and B in RESULT for easy debuggin'
- MOVWF RESULT
- ; Shift WREG to the left a bunch so that it fits
- ; correctly in PORTB
- RLNCF WREG
- RLNCF WREG
- RLNCF WREG
- RLNCF WREG
- MOVWF PORTB
- ; Set the last PORTB to this PORTB. This way,
- ; we can tell in the future if the inputs change.
- MOVFF PORTB, LAST
- ; Go back to the main loop
- GOTO Loop
- END
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