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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 15:03:30 12/18/2019
- -- Design Name:
- -- Module Name: zamekv2 - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity zamekv2 is
- Port ( Dio : in STD_LOGIC_VECTOR (7 downto 0);
- reset : in STD_LOGIC;
- E0 : in STD_LOGIC;
- F0 : in STD_LOGIC;
- dio_rdy : in STD_LOGIC;
- y : out STD_LOGIC;
- on_unlock : out STD_LOGIC;
- st : out STD_LOGIC_VECTOR (3 downto 0));
- end zamekv2;
- architecture Behavioral of zamekv2 is
- type state_type is (S0, S1, S2, S3, S4);
- signal state, next_state : state_type;
- begin
- SYNC_PROC : process (dio_rdy)
- begin
- if rising_edge(dio_rdy) then
- if (reset = '1') then
- state <= S0;
- elsif dio_rdy = '1' and F0 = '1' then
- state <= next_state;
- end if;
- end if;
- end process;
- OUTPUT_DECODE : process (state)
- begin
- case (state) is
- when S4 =>
- y <= '1';
- when others =>
- y <= '0';
- end case;
- end process;
- ST_DECODE : process (state)
- begin
- case (state) is
- when S0 =>
- st <= "0000" ;
- when S1 =>
- st <= "0001" ;
- when S2 =>
- st <= "0010" ;
- when S3 =>
- st <= "0011" ;
- when S4 =>
- st <= "0100" ;
- end case;
- end process;
- ON_UNLOCK_DECODE : process (state, F0, dio_rdy)
- begin
- IF (state = S4 AND F0 = '1' AND dio_rdy = '1') THEN
- on_unlock <= '1';
- else
- on_unlock <= '0';
- end IF;
- end process;
- NEXT_STATE_DECODE : process (state, dio)
- begin
- next_state <= S0;
- case (state) is
- when S0 =>
- if (dio = X"1D") then
- next_state <= S1;
- end if;
- when S1 =>
- if (dio = X"42") then
- next_state <= S2;
- elsif (dio = X"1D") then
- next_state <= S1;
- end if;
- when S2 =>
- if (dio = X"2B") then
- next_state <= S3;
- elsif (dio = X"1D") then
- next_state <= S1;
- end if;
- when S3 =>
- if (dio = X"1D") then
- next_state <= S4;
- end if;
- when S4 =>
- if (dio = X"42") then
- next_state <= S2;
- elsif (dio = X"1D") then
- next_state <= S1;
- end if;
- end case;
- end process;
- end architecture;
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