CAPI=1
[main]
description = "TCP/IP controlled VPI JTAG Interface"
simulators = icarus

[verilog]
tb_src_files = jtag_vpi.v
tb_private_src_files =
 bench/adv_debugsys/adbg_crc32.v
 bench/adv_debugsys/adbg_jsp_biu.v
 bench/adv_debugsys/adbg_jsp_module.v
 bench/adv_debugsys/adbg_or1k_biu.v
 bench/adv_debugsys/adbg_or1k_module.v
 bench/adv_debugsys/adbg_or1k_status_reg.v
 bench/adv_debugsys/adbg_wb_biu.v
 bench/adv_debugsys/adbg_wb_module.v
 bench/adv_debugsys/adv_dbg_if.v
 bench/adv_debugsys/bytefifo.v
 bench/adv_debugsys/syncflop.v
 bench/adv_debugsys/syncreg.v
 bench/jtag_tap/jtag_tap.v
 bench/ram/ram_wb_b3.v
 bench/jtag_vpi_tb.v
tb_include_files =
 bench/include/adbg_defines.v
 bench/include/adbg_or1k_defines.v
 bench/include/adbg_wb_defines.v
 bench/include/tap_defines.v
 bench/include/timescale.v

[vpi]
name = jtag_vpi
src_files = jtag_vpi.c

[plusargs]
jtag-vpi-enable = bool "Enable JTAG debug interface"

[provider]
name = github
user = fjullien
repo = jtag_vpi
branch = master