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  1. admin@miqi-6:~$ /tmp/tinymembench
  2. tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
  3.  
  4. ==========================================================================
  5. == Memory bandwidth tests ==
  6. == ==
  7. == Note 1: 1MB = 1000000 bytes ==
  8. == Note 2: Results for 'copy' tests show how many bytes can be ==
  9. == copied per second (adding together read and writen ==
  10. == bytes would have provided twice higher numbers) ==
  11. == Note 3: 2-pass copy means that we are using a small temporary buffer ==
  12. == to first fetch data into it, and only then write it to the ==
  13. == destination (source -> L1 cache, L1 cache -> destination) ==
  14. == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
  15. == brackets ==
  16. ==========================================================================
  17.  
  18. C copy backwards : 2145.1 MB/s
  19. C copy backwards (32 byte blocks) : 2184.9 MB/s
  20. C copy backwards (64 byte blocks) : 2178.6 MB/s
  21. C copy : 2205.8 MB/s
  22. C copy prefetched (32 bytes step) : 2388.3 MB/s
  23. C copy prefetched (64 bytes step) : 2548.0 MB/s (0.8%)
  24. C 2-pass copy : 1411.9 MB/s
  25. C 2-pass copy prefetched (32 bytes step) : 2193.4 MB/s
  26. C 2-pass copy prefetched (64 bytes step) : 2309.7 MB/s
  27. C fill : 6320.1 MB/s (0.2%)
  28. C fill (shuffle within 16 byte blocks) : 6294.2 MB/s (0.1%)
  29. C fill (shuffle within 32 byte blocks) : 6278.4 MB/s
  30. C fill (shuffle within 64 byte blocks) : 6286.3 MB/s
  31. ---
  32. standard memcpy : 2718.7 MB/s (2.6%)
  33. standard memset : 5474.8 MB/s (0.2%)
  34. ---
  35. NEON read : 6125.8 MB/s
  36. NEON read prefetched (32 bytes step) : 5943.5 MB/s
  37. NEON read prefetched (64 bytes step) : 6391.1 MB/s (0.3%)
  38. NEON read 2 data streams : 6628.1 MB/s (0.1%)
  39. NEON read 2 data streams prefetched (32 bytes step) : 5951.2 MB/s
  40. NEON read 2 data streams prefetched (64 bytes step) : 5893.8 MB/s
  41. NEON copy : 4046.0 MB/s
  42. NEON copy prefetched (32 bytes step) : 3513.1 MB/s (0.6%)
  43. NEON copy prefetched (64 bytes step) : 3285.3 MB/s
  44. NEON unrolled copy : 3981.8 MB/s
  45. NEON unrolled copy prefetched (32 bytes step) : 3750.4 MB/s (0.1%)
  46. NEON unrolled copy prefetched (64 bytes step) : 4057.0 MB/s
  47. NEON copy backwards : 4174.0 MB/s
  48. NEON copy backwards prefetched (32 bytes step) : 2803.7 MB/s (0.6%)
  49. NEON copy backwards prefetched (64 bytes step) : 2839.5 MB/s (0.2%)
  50. NEON 2-pass copy : 2147.1 MB/s
  51. NEON 2-pass copy prefetched (32 bytes step) : 2106.5 MB/s
  52. NEON 2-pass copy prefetched (64 bytes step) : 1759.2 MB/s
  53. NEON unrolled 2-pass copy : 2169.1 MB/s
  54. NEON unrolled 2-pass copy prefetched (32 bytes step) : 2118.9 MB/s (0.1%)
  55. NEON unrolled 2-pass copy prefetched (64 bytes step) : 2248.3 MB/s
  56. NEON fill : 6319.2 MB/s (0.2%)
  57. NEON fill backwards : 6289.2 MB/s
  58. VFP copy : 3976.7 MB/s
  59. VFP 2-pass copy : 2146.3 MB/s
  60. ARM fill (STRD) : 6298.0 MB/s (0.1%)
  61. ARM fill (STM with 8 registers) : 6295.0 MB/s (0.2%)
  62. ARM fill (STM with 4 registers) : 6292.4 MB/s
  63. ARM copy prefetched (incr pld) : 3743.6 MB/s
  64. ARM copy prefetched (wrap pld) : 3665.4 MB/s
  65. ARM 2-pass copy prefetched (incr pld) : 2057.8 MB/s
  66. ARM 2-pass copy prefetched (wrap pld) : 2030.8 MB/s
  67.  
  68. ==========================================================================
  69. == Memory latency test ==
  70. == ==
  71. == Average time is measured for random memory accesses in the buffers ==
  72. == of different sizes. The larger is the buffer, the more significant ==
  73. == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
  74. == accesses. For extremely large buffer sizes we are expecting to see ==
  75. == page table walk with several requests to SDRAM for almost every ==
  76. == memory access (though 64MiB is not nearly large enough to experience ==
  77. == this effect to its fullest). ==
  78. == ==
  79. == Note 1: All the numbers are representing extra time, which needs to ==
  80. == be added to L1 cache latency. The cycle timings for L1 cache ==
  81. == latency can be usually found in the processor documentation. ==
  82. == Note 2: Dual random read means that we are simultaneously performing ==
  83. == two independent memory accesses at a time. In the case if ==
  84. == the memory subsystem can't handle multiple outstanding ==
  85. == requests, dual random read has the same timings as two ==
  86. == single reads performed one after another. ==
  87. ==========================================================================
  88.  
  89. block size : single random read / dual random read
  90. 1024 : 0.0 ns / 0.0 ns
  91. 2048 : 0.0 ns / 0.0 ns
  92. 4096 : 0.0 ns / 0.0 ns
  93. 8192 : 0.0 ns / 0.0 ns
  94. 16384 : 0.0 ns / 0.0 ns
  95. 32768 : 0.0 ns / 0.0 ns
  96. 65536 : 6.2 ns / 10.6 ns
  97. 131072 : 9.2 ns / 14.6 ns
  98. 262144 : 12.5 ns / 17.8 ns
  99. 524288 : 14.1 ns / 19.4 ns
  100. 1048576 : 15.6 ns / 20.8 ns
  101. 2097152 : 51.7 ns / 75.2 ns
  102. 4194304 : 70.2 ns / 92.8 ns
  103. 8388608 : 83.8 ns / 103.6 ns
  104. 16777216 : 92.1 ns / 110.1 ns
  105. 33554432 : 98.5 ns / 116.2 ns
  106. 67108864 : 104.0 ns / 122.9 ns
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