module DFF(output reg Q, input D, CLK);
always @ (posedge CLK)
Q <= D;
endmodule

module testbench();
reg x;
reg y;
reg Da;
wire Qa;
reg Db;
wire Qb;
reg CLK;

DFF ffa(Qa, Da, CLK);
DFF ffb(Qb, Db, CLK);

initial begin
forever
begin
#1 CLK = 0 ;x=0;y=0;Da = ((x & !y) | (x & Qb));Db = ((x & Qa) | (x & !Qb));
#1 CLK = 1 ;$display("Qa|Qb|x|y|Qa(next)|Qb(next)|");
#1 CLK = 0 ;x=1;y=0;Da = ((x & !y) | (x & Qb));Db = ((x & Qa) | (x & !Qb));
#1 CLK = 1 ;$display("%2b|%2b|%b|%b|%8b|%8b|",Qa,Qb,x,y,Da,Db);
#1 CLK = 0 ;x=1;y=1;Da = ((x & !y) | (x & Qb));Db = ((x & Qa) | (x & !Qb));
#1 CLK = 1 ;$display("%2b|%2b|%b|%b|%8b|%8b|",Qa,Qb,x,y,Da,Db);
#1 CLK = 0 ;x=0;y=1;Da = ((x & !y) | (x & Qb));Db = ((x & Qa) | (x & !Qb));
#1 CLK = 1 ;$display("%2b|%2b|%b|%b|%8b|%8b|",Qa,Qb,x,y,Da,Db);
#1 CLK = 0 ;x=0;y=1;Da = ((x & !y) | (x & Qb));Db = ((x & Qa) | (x & !Qb));
#1 CLK = 1 ;$display("%2b|%2b|%b|%b|%8b|%8b|",Qa,Qb,x,y,Da,Db);
$finish;

end
end

endmodule