`timescale 1ns / 1ps

module my_and (a, b, out);

    input a, b;
    output out;

    wire tmp;

    supply0 gnd;
    supply1 vcc;

  assign out = tmp;

  nmos nmos1 (nout1, vcc, a);
  nmos nmos2 (tmp, nout1, b);

  pulldown pd1 (tmp);

endmodule