testbench_q1_lista03

-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
--
end testbench;

architecture comp of testbench is

component simple

port (
    clock, reset, w :   in std_logic;
    z:                  out std_logic
);
end component;

signal clk_signal, z_signal, w_signal, reset_signal :std_logic;

constant PERIODO : time := 10 ns;

begin

U0: simple Port map(
    clock => clk_signal,
    reset => reset_signal,
    z => z_signal,
    w => w_signal
);

    --Gerando o clock

    ClockGen: process
    begin
        for i in 0 to 10 loop
        clk_signal <= '0';
        wait for PERIODO;
        clk_signal <= '1';
        wait for PERIODO;
      end loop;
      wait;
    end process ClockGen;

    --Sinal da entrada w

    entradaB: process
    begin
      w_signal <= '0';
      wait for 2*PERIODO;
      w_signal <= '1';
      wait for 7*PERIODO;
      w_signal <= '0';
      wait for 2*PERIODO;
      w_signal <= '1';
      wait for 8*PERIODO;
      wait;
    end process entradaB;

    --Sinal do reset

    resetSignal: process
    begin
        reset_signal <= '0';
      wait for 2*PERIODO;
      reset_signal <= '1';
      wait for 10*PERIODO;
      reset_signal <= '0';
      wait for 2*PERIODO;
      reset_signal <= '1';
      wait for 2*PERIODO;
      wait;
    end process resetSignal;

end comp;