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safweneful
Apr 3rd, 2018
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x1>;
  5. #size-cells = <0x1>;
  6. compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
  7. model = "Zynq ZC702 Development Board";
  8.  
  9. cpus {
  10. #address-cells = <0x1>;
  11. #size-cells = <0x0>;
  12.  
  13. cpu@0 {
  14. compatible = "arm,cortex-a9";
  15. device_type = "cpu";
  16. reg = <0x0>;
  17. clocks = <0x1 0x3>;
  18. clock-latency = <0x3e8>;
  19. cpu0-supply = <0x2>;
  20. operating-points = <0xa2c2a 0xf4240 0x51615 0xf4240>;
  21. };
  22.  
  23. cpu@1 {
  24. compatible = "arm,cortex-a9";
  25. device_type = "cpu";
  26. reg = <0x1>;
  27. clocks = <0x1 0x3>;
  28. };
  29. };
  30.  
  31. fpga-full {
  32. compatible = "fpga-region";
  33. fpga-mgr = <0x3>;
  34. #address-cells = <0x1>;
  35. #size-cells = <0x1>;
  36. ranges;
  37. };
  38.  
  39. pmu@f8891000 {
  40. compatible = "arm,cortex-a9-pmu";
  41. interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
  42. interrupt-parent = <0x4>;
  43. reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
  44. };
  45.  
  46. fixedregulator {
  47. compatible = "regulator-fixed";
  48. regulator-name = "VCCPINT";
  49. regulator-min-microvolt = <0xf4240>;
  50. regulator-max-microvolt = <0xf4240>;
  51. regulator-boot-on;
  52. regulator-always-on;
  53. linux,phandle = <0x2>;
  54. phandle = <0x2>;
  55. };
  56.  
  57. amba {
  58. u-boot,dm-pre-reloc;
  59. compatible = "simple-bus";
  60. #address-cells = <0x1>;
  61. #size-cells = <0x1>;
  62. interrupt-parent = <0x4>;
  63. ranges;
  64.  
  65. adc@f8007100 {
  66. compatible = "xlnx,zynq-xadc-1.00.a";
  67. reg = <0xf8007100 0x20>;
  68. interrupts = <0x0 0x7 0x4>;
  69. interrupt-parent = <0x4>;
  70. clocks = <0x1 0xc>;
  71. };
  72.  
  73. can@e0008000 {
  74. compatible = "xlnx,zynq-can-1.0";
  75. status = "okay";
  76. clocks = <0x1 0x13 0x1 0x24>;
  77. clock-names = "can_clk", "pclk";
  78. reg = <0xe0008000 0x1000>;
  79. interrupts = <0x0 0x1c 0x4>;
  80. interrupt-parent = <0x4>;
  81. tx-fifo-depth = <0x40>;
  82. rx-fifo-depth = <0x40>;
  83. pinctrl-names = "default";
  84. pinctrl-0 = <0x5>;
  85. };
  86.  
  87. can@e0009000 {
  88. compatible = "xlnx,zynq-can-1.0";
  89. status = "disabled";
  90. clocks = <0x1 0x14 0x1 0x25>;
  91. clock-names = "can_clk", "pclk";
  92. reg = <0xe0009000 0x1000>;
  93. interrupts = <0x0 0x33 0x4>;
  94. interrupt-parent = <0x4>;
  95. tx-fifo-depth = <0x40>;
  96. rx-fifo-depth = <0x40>;
  97. };
  98.  
  99. gpio@e000a000 {
  100. compatible = "xlnx,zynq-gpio-1.0";
  101. #gpio-cells = <0x2>;
  102. clocks = <0x1 0x2a>;
  103. gpio-controller;
  104. interrupt-controller;
  105. #interrupt-cells = <0x2>;
  106. interrupt-parent = <0x4>;
  107. interrupts = <0x0 0x14 0x4>;
  108. reg = <0xe000a000 0x1000>;
  109. pinctrl-names = "default";
  110. pinctrl-0 = <0x6>;
  111. emio-gpio-width = <0x40>;
  112. gpio-mask-high = <0x0>;
  113. gpio-mask-low = <0x5600>;
  114. linux,phandle = <0x9>;
  115. phandle = <0x9>;
  116. };
  117.  
  118. i2c@e0004000 {
  119. compatible = "cdns,i2c-r1p10";
  120. status = "okay";
  121. clocks = <0x1 0x26>;
  122. interrupt-parent = <0x4>;
  123. interrupts = <0x0 0x19 0x4>;
  124. reg = <0xe0004000 0x1000>;
  125. #address-cells = <0x1>;
  126. #size-cells = <0x0>;
  127. pinctrl-names = "default", "gpio";
  128. pinctrl-0 = <0x7>;
  129. pinctrl-1 = <0x8>;
  130. scl-gpios = <0x9 0x32 0x0>;
  131. sda-gpios = <0x9 0x33 0x0>;
  132. clock-frequency = <0x61a80>;
  133. i2c-reset = <0x9 0xd 0x0>;
  134.  
  135. i2cswitch@74 {
  136. compatible = "nxp,pca9548";
  137. #address-cells = <0x1>;
  138. #size-cells = <0x0>;
  139. reg = <0x74>;
  140.  
  141. i2c@0 {
  142. #address-cells = <0x1>;
  143. #size-cells = <0x0>;
  144. reg = <0x0>;
  145.  
  146. clock-generator@5d {
  147. #clock-cells = <0x0>;
  148. compatible = "silabs,si570";
  149. temperature-stability = <0x32>;
  150. reg = <0x5d>;
  151. factory-fout = <0x9502f90>;
  152. clock-frequency = <0x8d9ee20>;
  153. };
  154. };
  155.  
  156. i2c@1 {
  157. #address-cells = <0x1>;
  158. #size-cells = <0x0>;
  159. reg = <0x1>;
  160.  
  161. hdmi-tx@39 {
  162. compatible = "adi,adv7511";
  163. reg = <0x39>;
  164. adi,input-depth = <0x8>;
  165. adi,input-colorspace = "yuv422";
  166. adi,input-clock = "1x";
  167. adi,input-style = <0x3>;
  168. adi,input-justification = "right";
  169. };
  170. };
  171.  
  172. i2c@2 {
  173. #address-cells = <0x1>;
  174. #size-cells = <0x0>;
  175. reg = <0x2>;
  176.  
  177. eeprom@54 {
  178. compatible = "at,24c08";
  179. reg = <0x54>;
  180. };
  181. };
  182.  
  183. i2c@3 {
  184. #address-cells = <0x1>;
  185. #size-cells = <0x0>;
  186. reg = <0x3>;
  187.  
  188. gpio@21 {
  189. compatible = "ti,tca6416";
  190. reg = <0x21>;
  191. gpio-controller;
  192. #gpio-cells = <0x2>;
  193. };
  194. };
  195.  
  196. i2c@4 {
  197. #address-cells = <0x1>;
  198. #size-cells = <0x0>;
  199. reg = <0x4>;
  200.  
  201. rtc@51 {
  202. compatible = "nxp,pcf8563";
  203. reg = <0x51>;
  204. };
  205. };
  206.  
  207. i2c@7 {
  208. #address-cells = <0x1>;
  209. #size-cells = <0x0>;
  210. reg = <0x7>;
  211.  
  212. hwmon@52 {
  213. compatible = "ti,ucd9248";
  214. reg = <0x34>;
  215. };
  216.  
  217. hwmon@53 {
  218. compatible = "ti,ucd9248";
  219. reg = <0x35>;
  220. };
  221.  
  222. hwmon@54 {
  223. compatible = "ti,ucd9248";
  224. reg = <0x36>;
  225. };
  226. };
  227. };
  228. };
  229.  
  230. i2c@e0005000 {
  231. compatible = "cdns,i2c-r1p10";
  232. status = "disabled";
  233. clocks = <0x1 0x27>;
  234. interrupt-parent = <0x4>;
  235. interrupts = <0x0 0x30 0x4>;
  236. reg = <0xe0005000 0x1000>;
  237. #address-cells = <0x1>;
  238. #size-cells = <0x0>;
  239. };
  240.  
  241. interrupt-controller@f8f01000 {
  242. compatible = "arm,cortex-a9-gic";
  243. #interrupt-cells = <0x3>;
  244. interrupt-controller;
  245. reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
  246. num_cpus = <0x2>;
  247. num_interrupts = <0x60>;
  248. linux,phandle = <0x4>;
  249. phandle = <0x4>;
  250. };
  251.  
  252. cache-controller@f8f02000 {
  253. compatible = "arm,pl310-cache";
  254. reg = <0xf8f02000 0x1000>;
  255. interrupts = <0x0 0x2 0x4>;
  256. arm,data-latency = <0x3 0x2 0x2>;
  257. arm,tag-latency = <0x2 0x2 0x2>;
  258. cache-unified;
  259. cache-level = <0x2>;
  260. };
  261.  
  262. memory-controller@f8006000 {
  263. compatible = "xlnx,zynq-ddrc-a05";
  264. reg = <0xf8006000 0x1000>;
  265. };
  266.  
  267. ocmc@f800c000 {
  268. compatible = "xlnx,zynq-ocmc-1.0";
  269. interrupt-parent = <0x4>;
  270. interrupts = <0x0 0x3 0x4>;
  271. reg = <0xf800c000 0x1000>;
  272. };
  273.  
  274. serial@e0000000 {
  275. compatible = "xlnx,xuartps", "cdns,uart-r1p8";
  276. status = "disabled";
  277. clocks = <0x1 0x17 0x1 0x28>;
  278. clock-names = "uart_clk", "pclk";
  279. reg = <0xe0000000 0x1000>;
  280. interrupts = <0x0 0x1b 0x4>;
  281. };
  282.  
  283. serial@e0001000 {
  284. compatible = "xlnx,xuartps", "cdns,uart-r1p8";
  285. status = "okay";
  286. clocks = <0x1 0x18 0x1 0x29>;
  287. clock-names = "uart_clk", "pclk";
  288. reg = <0xe0001000 0x1000>;
  289. interrupts = <0x0 0x32 0x4>;
  290. u-boot,dm-pre-reloc;
  291. pinctrl-names = "default";
  292. pinctrl-0 = <0xa>;
  293. device_type = "serial";
  294. port-number = <0x0>;
  295. };
  296.  
  297. spi@e0006000 {
  298. compatible = "xlnx,zynq-spi-r1p6";
  299. reg = <0xe0006000 0x1000>;
  300. status = "disabled";
  301. interrupt-parent = <0x4>;
  302. interrupts = <0x0 0x1a 0x4>;
  303. clocks = <0x1 0x19 0x1 0x22>;
  304. clock-names = "ref_clk", "pclk";
  305. #address-cells = <0x1>;
  306. #size-cells = <0x0>;
  307. };
  308.  
  309. spi@e0007000 {
  310. compatible = "xlnx,zynq-spi-r1p6";
  311. reg = <0xe0007000 0x1000>;
  312. status = "disabled";
  313. interrupt-parent = <0x4>;
  314. interrupts = <0x0 0x31 0x4>;
  315. clocks = <0x1 0x1a 0x1 0x23>;
  316. clock-names = "ref_clk", "pclk";
  317. #address-cells = <0x1>;
  318. #size-cells = <0x0>;
  319. };
  320.  
  321. spi@e000d000 {
  322. clock-names = "ref_clk", "pclk";
  323. clocks = <0x1 0xa 0x1 0x2b>;
  324. compatible = "xlnx,zynq-qspi-1.0";
  325. status = "okay";
  326. interrupt-parent = <0x4>;
  327. interrupts = <0x0 0x13 0x4>;
  328. reg = <0xe000d000 0x1000>;
  329. #address-cells = <0x1>;
  330. #size-cells = <0x0>;
  331. u-boot,dm-pre-reloc;
  332. is-dual = <0x0>;
  333. num-cs = <0x1>;
  334. spi-rx-bus-width = <0x4>;
  335. spi-tx-bus-width = <0x4>;
  336.  
  337. flash@0 {
  338. compatible = "n25q512a", "micron,m25p80";
  339. reg = <0x0>;
  340. spi-tx-bus-width = <0x1>;
  341. spi-rx-bus-width = <0x4>;
  342. spi-max-frequency = <0x2faf080>;
  343. #address-cells = <0x1>;
  344. #size-cells = <0x1>;
  345.  
  346. partition@0x00000000 {
  347. label = "boot";
  348. reg = <0x0 0x500000>;
  349. };
  350.  
  351. partition@0x00500000 {
  352. label = "bootenv";
  353. reg = <0x500000 0x20000>;
  354. };
  355.  
  356. partition@0x00520000 {
  357. label = "kernel";
  358. reg = <0x520000 0xa80000>;
  359. };
  360.  
  361. partition@0x00fa0000 {
  362. label = "spare";
  363. reg = <0xfa0000 0x0>;
  364. };
  365. };
  366. };
  367.  
  368. memory-controller@e000e000 {
  369. #address-cells = <0x1>;
  370. #size-cells = <0x1>;
  371. status = "disabled";
  372. clock-names = "memclk", "aclk";
  373. clocks = <0x1 0xb 0x1 0x2c>;
  374. compatible = "arm,pl353-smc-r2p1";
  375. interrupt-parent = <0x4>;
  376. interrupts = <0x0 0x12 0x4>;
  377. ranges;
  378. reg = <0xe000e000 0x1000>;
  379.  
  380. flash@e1000000 {
  381. status = "disabled";
  382. compatible = "arm,pl353-nand-r2p1";
  383. reg = <0xe1000000 0x1000000>;
  384. #address-cells = <0x1>;
  385. #size-cells = <0x1>;
  386. };
  387.  
  388. flash@e2000000 {
  389. status = "disabled";
  390. compatible = "cfi-flash";
  391. reg = <0xe2000000 0x2000000>;
  392. #address-cells = <0x1>;
  393. #size-cells = <0x1>;
  394. };
  395. };
  396.  
  397. ethernet@e000b000 {
  398. compatible = "cdns,zynq-gem", "cdns,gem";
  399. reg = <0xe000b000 0x1000>;
  400. status = "okay";
  401. interrupts = <0x0 0x16 0x4>;
  402. clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>;
  403. clock-names = "pclk", "hclk", "tx_clk";
  404. #address-cells = <0x1>;
  405. #size-cells = <0x0>;
  406. phy-handle = <0xb>;
  407. pinctrl-names = "default";
  408. pinctrl-0 = <0xc>;
  409. phy-reset-gpio = <0x9 0xb 0x0>;
  410. phy-reset-active-low;
  411. enet-reset = <0x9 0xb 0x0>;
  412. phy-mode = "rgmii-id";
  413. xlnx,ptp-enet-clock = <0x69f6bcb>;
  414. local-mac-address = [00 0a 35 00 1e 53];
  415.  
  416. ethernet-phy@7 {
  417. reg = <0x7>;
  418. device_type = "ethernet-phy";
  419. linux,phandle = <0xb>;
  420. phandle = <0xb>;
  421. };
  422. };
  423.  
  424. ethernet@e000c000 {
  425. compatible = "cdns,zynq-gem", "cdns,gem";
  426. reg = <0xe000c000 0x1000>;
  427. status = "disabled";
  428. interrupts = <0x0 0x2d 0x4>;
  429. clocks = <0x1 0x1f 0x1 0x1f 0x1 0xe>;
  430. clock-names = "pclk", "hclk", "tx_clk";
  431. #address-cells = <0x1>;
  432. #size-cells = <0x0>;
  433. };
  434.  
  435. sdhci@e0100000 {
  436. compatible = "arasan,sdhci-8.9a";
  437. status = "okay";
  438. clock-names = "clk_xin", "clk_ahb";
  439. clocks = <0x1 0x15 0x1 0x20>;
  440. interrupt-parent = <0x4>;
  441. interrupts = <0x0 0x18 0x4>;
  442. reg = <0xe0100000 0x1000>;
  443. broken-adma2;
  444. u-boot,dm-pre-reloc;
  445. pinctrl-names = "default";
  446. pinctrl-0 = <0xd>;
  447. xlnx,has-cd = <0x1>;
  448. xlnx,has-power = <0x0>;
  449. xlnx,has-wp = <0x1>;
  450. };
  451.  
  452. sdhci@e0101000 {
  453. compatible = "arasan,sdhci-8.9a";
  454. status = "disabled";
  455. clock-names = "clk_xin", "clk_ahb";
  456. clocks = <0x1 0x16 0x1 0x21>;
  457. interrupt-parent = <0x4>;
  458. interrupts = <0x0 0x2f 0x4>;
  459. reg = <0xe0101000 0x1000>;
  460. broken-adma2;
  461. };
  462.  
  463. slcr@f8000000 {
  464. #address-cells = <0x1>;
  465. #size-cells = <0x1>;
  466. compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
  467. reg = <0xf8000000 0x1000>;
  468. ranges;
  469. linux,phandle = <0xe>;
  470. phandle = <0xe>;
  471.  
  472. clkc@100 {
  473. #clock-cells = <0x1>;
  474. compatible = "xlnx,ps7-clkc";
  475. fclk-enable = <0x1>;
  476. clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
  477. reg = <0x100 0x100>;
  478. ps-clk-frequency = <0x1fca055>;
  479. linux,phandle = <0x1>;
  480. phandle = <0x1>;
  481. };
  482.  
  483. rstc@200 {
  484. compatible = "xlnx,zynq-reset";
  485. reg = <0x200 0x48>;
  486. #reset-cells = <0x1>;
  487. syscon = <0xe>;
  488. };
  489.  
  490. pinctrl@700 {
  491. compatible = "xlnx,pinctrl-zynq";
  492. reg = <0x700 0x200>;
  493. syscon = <0xe>;
  494.  
  495. can0-default {
  496. linux,phandle = <0x5>;
  497. phandle = <0x5>;
  498.  
  499. mux {
  500. function = "can0";
  501. groups = "can0_9_grp";
  502. };
  503.  
  504. conf {
  505. groups = "can0_9_grp";
  506. slew-rate = <0x0>;
  507. io-standard = <0x1>;
  508. };
  509.  
  510. conf-rx {
  511. pins = "MIO46";
  512. bias-high-impedance;
  513. };
  514.  
  515. conf-tx {
  516. pins = "MIO47";
  517. bias-disable;
  518. };
  519. };
  520.  
  521. gem0-default {
  522. linux,phandle = <0xc>;
  523. phandle = <0xc>;
  524.  
  525. mux {
  526. function = "ethernet0";
  527. groups = "ethernet0_0_grp";
  528. };
  529.  
  530. conf {
  531. groups = "ethernet0_0_grp";
  532. slew-rate = <0x0>;
  533. io-standard = <0x4>;
  534. };
  535.  
  536. conf-rx {
  537. pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
  538. bias-high-impedance;
  539. low-power-disable;
  540. };
  541.  
  542. conf-tx {
  543. pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
  544. bias-disable;
  545. low-power-enable;
  546. };
  547.  
  548. mux-mdio {
  549. function = "mdio0";
  550. groups = "mdio0_0_grp";
  551. };
  552.  
  553. conf-mdio {
  554. groups = "mdio0_0_grp";
  555. slew-rate = <0x0>;
  556. io-standard = <0x1>;
  557. bias-disable;
  558. };
  559. };
  560.  
  561. gpio0-default {
  562. linux,phandle = <0x6>;
  563. phandle = <0x6>;
  564.  
  565. mux {
  566. function = "gpio0";
  567. groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp";
  568. };
  569.  
  570. conf {
  571. groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp";
  572. slew-rate = <0x0>;
  573. io-standard = <0x1>;
  574. };
  575.  
  576. conf-pull-up {
  577. pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
  578. bias-pull-up;
  579. };
  580.  
  581. conf-pull-none {
  582. pins = "MIO7", "MIO8";
  583. bias-disable;
  584. };
  585. };
  586.  
  587. i2c0-default {
  588. linux,phandle = <0x7>;
  589. phandle = <0x7>;
  590.  
  591. mux {
  592. groups = "i2c0_10_grp";
  593. function = "i2c0";
  594. };
  595.  
  596. conf {
  597. groups = "i2c0_10_grp";
  598. bias-pull-up;
  599. slew-rate = <0x0>;
  600. io-standard = <0x1>;
  601. };
  602. };
  603.  
  604. i2c0-gpio {
  605. linux,phandle = <0x8>;
  606. phandle = <0x8>;
  607.  
  608. mux {
  609. groups = "gpio0_50_grp", "gpio0_51_grp";
  610. function = "gpio0";
  611. };
  612.  
  613. conf {
  614. groups = "gpio0_50_grp", "gpio0_51_grp";
  615. slew-rate = <0x0>;
  616. io-standard = <0x1>;
  617. };
  618. };
  619.  
  620. sdhci0-default {
  621. linux,phandle = <0xd>;
  622. phandle = <0xd>;
  623.  
  624. mux {
  625. groups = "sdio0_2_grp";
  626. function = "sdio0";
  627. };
  628.  
  629. conf {
  630. groups = "sdio0_2_grp";
  631. slew-rate = <0x0>;
  632. io-standard = <0x1>;
  633. bias-disable;
  634. };
  635.  
  636. mux-cd {
  637. groups = "gpio0_0_grp";
  638. function = "sdio0_cd";
  639. };
  640.  
  641. conf-cd {
  642. groups = "gpio0_0_grp";
  643. bias-high-impedance;
  644. bias-pull-up;
  645. slew-rate = <0x0>;
  646. io-standard = <0x1>;
  647. };
  648.  
  649. mux-wp {
  650. groups = "gpio0_15_grp";
  651. function = "sdio0_wp";
  652. };
  653.  
  654. conf-wp {
  655. groups = "gpio0_15_grp";
  656. bias-high-impedance;
  657. bias-pull-up;
  658. slew-rate = <0x0>;
  659. io-standard = <0x1>;
  660. };
  661. };
  662.  
  663. uart1-default {
  664. linux,phandle = <0xa>;
  665. phandle = <0xa>;
  666.  
  667. mux {
  668. groups = "uart1_10_grp";
  669. function = "uart1";
  670. };
  671.  
  672. conf {
  673. groups = "uart1_10_grp";
  674. slew-rate = <0x0>;
  675. io-standard = <0x1>;
  676. };
  677.  
  678. conf-rx {
  679. pins = "MIO49";
  680. bias-high-impedance;
  681. };
  682.  
  683. conf-tx {
  684. pins = "MIO48";
  685. bias-disable;
  686. };
  687. };
  688.  
  689. usb0-default {
  690. linux,phandle = <0x10>;
  691. phandle = <0x10>;
  692.  
  693. mux {
  694. groups = "usb0_0_grp";
  695. function = "usb0";
  696. };
  697.  
  698. conf {
  699. groups = "usb0_0_grp";
  700. slew-rate = <0x0>;
  701. io-standard = <0x1>;
  702. };
  703.  
  704. conf-rx {
  705. pins = "MIO29", "MIO31", "MIO36";
  706. bias-high-impedance;
  707. };
  708.  
  709. conf-tx {
  710. pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39";
  711. bias-disable;
  712. };
  713. };
  714. };
  715. };
  716.  
  717. dmac@f8003000 {
  718. compatible = "arm,pl330", "arm,primecell";
  719. reg = <0xf8003000 0x1000>;
  720. interrupt-parent = <0x4>;
  721. interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
  722. interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
  723. #dma-cells = <0x1>;
  724. #dma-channels = <0x8>;
  725. #dma-requests = <0x4>;
  726. clocks = <0x1 0x1b>;
  727. clock-names = "apb_pclk";
  728. };
  729.  
  730. devcfg@f8007000 {
  731. compatible = "xlnx,zynq-devcfg-1.0";
  732. interrupt-parent = <0x4>;
  733. interrupts = <0x0 0x8 0x4>;
  734. reg = <0xf8007000 0x100>;
  735. clocks = <0x1 0xc 0x1 0xf 0x1 0x10 0x1 0x11 0x1 0x12>;
  736. clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
  737. syscon = <0xe>;
  738. linux,phandle = <0x3>;
  739. phandle = <0x3>;
  740. };
  741.  
  742. efuse@f800d000 {
  743. compatible = "xlnx,zynq-efuse";
  744. reg = <0xf800d000 0x20>;
  745. };
  746.  
  747. timer@f8f00200 {
  748. compatible = "arm,cortex-a9-global-timer";
  749. reg = <0xf8f00200 0x20>;
  750. interrupts = <0x1 0xb 0x301>;
  751. interrupt-parent = <0x4>;
  752. clocks = <0x1 0x4>;
  753. };
  754.  
  755. timer@f8001000 {
  756. interrupt-parent = <0x4>;
  757. interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
  758. compatible = "cdns,ttc";
  759. clocks = <0x1 0x6>;
  760. reg = <0xf8001000 0x1000>;
  761. };
  762.  
  763. timer@f8002000 {
  764. interrupt-parent = <0x4>;
  765. interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
  766. compatible = "cdns,ttc";
  767. clocks = <0x1 0x6>;
  768. reg = <0xf8002000 0x1000>;
  769. };
  770.  
  771. timer@f8f00600 {
  772. interrupt-parent = <0x4>;
  773. interrupts = <0x1 0xd 0x301>;
  774. compatible = "arm,cortex-a9-twd-timer";
  775. reg = <0xf8f00600 0x20>;
  776. clocks = <0x1 0x4>;
  777. };
  778.  
  779. usb@e0002000 {
  780. compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
  781. status = "okay";
  782. clocks = <0x1 0x1c>;
  783. interrupt-parent = <0x4>;
  784. interrupts = <0x0 0x15 0x4>;
  785. reg = <0xe0002000 0x1000>;
  786. phy_type = "ulpi";
  787. dr_mode = "host";
  788. usb-phy = <0xf>;
  789. pinctrl-names = "default";
  790. pinctrl-0 = <0x10>;
  791. usb-reset = <0x9 0x7 0x0>;
  792. };
  793.  
  794. usb@e0003000 {
  795. compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
  796. status = "disabled";
  797. clocks = <0x1 0x1d>;
  798. interrupt-parent = <0x4>;
  799. interrupts = <0x0 0x2c 0x4>;
  800. reg = <0xe0003000 0x1000>;
  801. phy_type = "ulpi";
  802. };
  803.  
  804. watchdog@f8005000 {
  805. clocks = <0x1 0x2d>;
  806. compatible = "cdns,wdt-r1p2";
  807. interrupt-parent = <0x4>;
  808. interrupts = <0x0 0x9 0x1>;
  809. reg = <0xf8005000 0x1000>;
  810. timeout-sec = <0xa>;
  811. };
  812. };
  813.  
  814. gpio-keys {
  815. compatible = "gpio-keys";
  816. #address-cells = <0x1>;
  817. #size-cells = <0x0>;
  818. autorepeat;
  819.  
  820. sw14 {
  821. label = "sw14";
  822. gpios = <0x9 0xc 0x0>;
  823. linux,code = <0x6c>;
  824. wakeup-source;
  825. autorepeat;
  826. };
  827.  
  828. sw13 {
  829. label = "sw13";
  830. gpios = <0x9 0xe 0x0>;
  831. linux,code = <0x67>;
  832. wakeup-source;
  833. autorepeat;
  834. };
  835. };
  836.  
  837. leds {
  838. compatible = "gpio-leds";
  839.  
  840. ds23 {
  841. label = "ds23";
  842. gpios = <0x9 0xa 0x0>;
  843. linux,default-trigger = "heartbeat";
  844. };
  845. };
  846.  
  847. phy0@e0002000 {
  848. compatible = "ulpi-phy";
  849. #phy-cells = <0x0>;
  850. reg = <0xe0002000 0x1000>;
  851. view-port = <0x170>;
  852. drv-vbus;
  853. linux,phandle = <0xf>;
  854. phandle = <0xf>;
  855. };
  856.  
  857. amba_pl {
  858. #address-cells = <0x1>;
  859. #size-cells = <0x1>;
  860. compatible = "simple-bus";
  861. ranges;
  862.  
  863.  
  864. dma@40400000 {
  865. reg = <0x40400000 0x10000>;
  866. interrupts = <0x0 0x3a 0x4 0x0 0x3b 0x4>;
  867. compatible = "xlnx,axi-dma-1.00.a";
  868. interrupt-parent = <0x3>;
  869.  
  870. dma-channels@40400000 {
  871. interrupts = <0x0 0x3a 0x4>;
  872. compatible = "xlnx,axi-dma-mm2s-channel";
  873. xlnx,device-id = <0x0>;
  874. xlnx,datawidth = <0x20>;
  875. };
  876.  
  877. dma-channels@40400030 {
  878. interrupts = <0x0 0x3b 0x4>;
  879. compatible = "xlnx,axi-dma-s2mm-channel";
  880. xlnx,device-id = <0x1>;
  881. xlnx,datawidth = <0x20>;
  882. };
  883. };
  884.  
  885. AXI_REG@83c00000 {
  886. reg = <0x83c00000 0x10000>;
  887. interrupts = <0x0 0x1d 0x4 0x0 0x1e 0x4 0x0 0x1f 0x4 0x0 0x20 0x4 0x0 0x21 0x4 0x0 0x22 0x4 0x0 0x23 0x4 0x0 0x24 0x4 0x0 0x34 0x4 0x0 0x35 0x4 0x0 0x36 0x4 0x0 0x37 0x4 0x0 0x38 0x4 0x0 0x39 0x4>;
  888. xlnx,s00-axi-addr-width = <0x12>;
  889. compatible = "xlnx,AXI-REG-1.0";
  890. xlnx,s00-axi-data-width = <0x20>;
  891. interrupt-parent = <0x3>;
  892. };
  893.  
  894.  
  895. gpio@41200000 {
  896. #gpio-cells = <0x2>;
  897. compatible = "xlnx,xps-gpio-1.00.a";
  898. gpio-controller;
  899. reg = <0x41200000 0x10000>;
  900. xlnx,all-inputs = <0x0>;
  901. xlnx,all-inputs-2 = <0x0>;
  902. xlnx,all-outputs = <0x1>;
  903. xlnx,all-outputs-2 = <0x0>;
  904. xlnx,dout-default = <0x0>;
  905. xlnx,dout-default-2 = <0x0>;
  906. xlnx,gpio-width = <0x4>;
  907. xlnx,gpio2-width = <0x20>;
  908. xlnx,interrupt-present = <0x0>;
  909. xlnx,is-dual = <0x0>;
  910. xlnx,tri-default = <0xffffffff>;
  911. xlnx,tri-default-2 = <0xffffffff>;
  912. };
  913. };
  914.  
  915. chosen {
  916. bootargs = "console=ttyPS0,115200 earlyprintk";
  917. stdout-path = "serial0:115200n8";
  918. };
  919.  
  920. aliases {
  921. ethernet0 = "/amba/ethernet@e000b000";
  922. serial0 = "/amba/serial@e0001000";
  923. spi0 = "/amba/spi@e000d000";
  924. };
  925.  
  926. memory {
  927. device_type = "memory";
  928. reg = <0x0 0x40000000>;
  929. };
  930. };
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