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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- package tipos is
- constant bandas : positive := 4;
- type vector32 is array (0 to bandas-1) of signed (31 downto 0);
- end package tipos;
- library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.numeric_std.all;
- library work; use work.tipos.all;
- package propios is
- --function declaration.
- function module (a : vector32; bands: natural) return unsigned;
- end propios; --end of package.
- package body propios is --start of package body
- --definition of function
- --based on: https://en.m.wikipedia.org/wiki/Methods_of_computing_square_roots#Binary_numeral_system_.28base_2.29
- function module (a : vector32; bands: natural) return unsigned is --To adapt it to a diferent number of bits in the input vector:
- --substitute the 71 for the needed number. Number of bits in each element of the vector *2 + power of two that can represent the maximum
- --number of bands, or fields. In this case, 32bit numbers, maximum number of bands, 256, so 2^8. 32*2+8=72.
- variable sum : unsigned(71 downto 0):= (others => '0');
- variable b : unsigned(71 downto 0):=(0=>'0', 70 => '1', others => '0');
- variable a_unsig: unsigned(31 downto 0):=(others =>'0');--for this vector use the same length as the input vector, 32bit in my case.
- variable result: unsigned (71 downto 0):= (others => '0');
- begin
- for i in 0 to bands-1 loop--Sum of all the elements squared
- a_unsig:=unsigned(a(i));
- sum:=sum + (a_unsig * a_unsig);
- end loop;
- --Square root of sum
- while b>sum loop--Do any needed changes here. You only have to change the 71's
- b:='0'&'0'& b(71 downto 2);
- end loop;
- while (b/=0) loop
- if (sum>=result+b) then
- sum:=sum - (result + b);
- result:=('0'& result(71 downto 1))+b;
- else
- result:='0'& result(71 downto 1);
- end if;
- b:='0' & '0' & b(71 downto 2);
- end loop;
- return result(35 downto 0);--sqrt(2^72)=2^36. Use half of the bits you put in place of 71
- end module;
- end propios; --end of the package body
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- library work;
- use work.propios.all;
- use work.tipos.all;
- ENTITY test IS
- END test;
- Architecture simple of test is
- signal a:vector32;
- signal c: unsigned(35 downto 0);
- signal b: natural:= 4;
- begin
- a(0)<="00000000110010011010011100000000";
- a(1)<="00000000110010011010011100000000";
- a(2)<="00000000110010011010011100000000";
- a(3)<="00000000110010011010011100000000";
- process
- begin
- wait for 200ps;
- c<= module (a , b);
- wait;
- end process;
- end simple;
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