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Oct 25th, 2018
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  1. module multT (
  2.     input signed [31:0]M,
  3.     input signed [31:0]Q,
  4.     input MultiCon,
  5.     input clk,
  6.     input reset,
  7.     output reg signed [31:0]hi,
  8.     output reg signed [31:0]lo
  9. );
  10.  
  11. reg signed [64:0]A;
  12. reg signed [64:0]S;
  13. reg signed [64:0]P;
  14. reg signed [31:0]aux;
  15. integer i;
  16.  
  17. always @ (posedge clk) begin
  18.     if (reset == 1) begin
  19.         A = 65'd0;
  20.         S = 65'd0;
  21.         P = 65'd0;
  22.         aux = 32'd0;
  23.         i = 0;
  24.     end
  25.     if (MultiCon == 1) begin
  26.         /*if (i > 31) begin
  27.  
  28.         end*/
  29.         A = {Q, 33'b0};
  30.         aux = ~Q + 1;
  31.         S = {aux, 33'b0};
  32.         P = {32'b0, M, 1'b0};
  33.         i = 0;
  34.     end
  35.     if (i < 32) begin
  36.         case (P[1:0])
  37.         2'b01: begin
  38.             P = P + A;
  39.         end
  40.         2'b10: begin
  41.             P = P + S;
  42.         end
  43.         endcase
  44.         P = P >>> 1;
  45.         i = i + 1;
  46.         hi = i;
  47.         if (i == 32) begin
  48.             hi = P[64:33];
  49.             lo = P[32:1];
  50.         end
  51.     end
  52. end
  53.  
  54. endmodule //
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