1:4 Demultiplexer Testbench

module demux_14_tst();
  reg a;
  reg [1:0]s;
  wire [3:0]c;

  demux_4to1 uut (.a(a),.s(s),.c(c));
  initial begin
          a = 1 ; s = 2'b00;
    #10   a = 1 ; s = 2'b01;
    #10   a = 1 ; s = 2'b10;
    #10   a = 1 ; s = 2'b11;
    #10   a = 0 ; s = 2'bxx;
  end
endmodule