module v_5_1(
    input clk,
    input BTN2,
    output reg[7:4] LED
    )
    reg [25:0] Q = 0;
    always @ (posedge clk)
        if(BTN2)
                cnt<=4'b0000;
        else
            if(Q==49999999)
                LED<={LED[2:0],~LED[3]};
                Q<=0;
            else
                Q<=Q+1;
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module v_5_2(
    input clk,
    input SW7,
    output [3:0] AN,
    output reg [6:0] SEG
    );
    reg [3:0] cnt;
    reg [25:0] Q = 0;
    assign AN=4'b1110;
    always @ (posedge clk)
        if(SW7==0)
            cnt<=0;
        else
            if(Q==/*49999999*/2)
            begin
                cnt<=cnt+1;
                Q<=0;
            end
            else
                Q<=Q+1;
   always @(cnt)
      case (cnt)
          4'b0001 : SEG = 7'b1111001;   // 1
          4'b0010 : SEG = 7'b0100100;   // 2
          4'b0011 : SEG = 7'b0110000;   // 3
          4'b0100 : SEG = 7'b0011001;   // 4
          4'b0101 : SEG = 7'b0010010;   // 5
          4'b0110 : SEG = 7'b0000010;   // 6
          4'b0111 : SEG = 7'b1111000;   // 7
          4'b1000 : SEG = 7'b0000000;   // 8
          4'b1001 : SEG = 7'b0010000;   // 9
          4'b1010 : SEG = 7'b0001000;   // A
          4'b1011 : SEG = 7'b0000011;   // b
          4'b1100 : SEG = 7'b1000110;   // C
          4'b1101 : SEG = 7'b0100001;   // d
          4'b1110 : SEG = 7'b0000110;   // E
          4'b1111 : SEG = 7'b0001110;   // F
          default : SEG = 7'b1000000;   // 0
      endcase
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module v_5_3(
    input clk,
    input SW1,
    output reg[7:4] LED
    );
reg [25:0] Q = 0;
always @ (posedge clk)
    if (SW1==0)
        LED<=4'b1000;
    else
        if(Q==49999999)
            begin
                LED<={LED[4],LED[7:5]};
                Q<=0;
            end
        else
            Q<=Q+1;
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module v_5_4(
    input clk,
    input SW0,
    output reg[7:4] LED) ;
reg [25:0] Q =0;
reg [3:1] cntr;
always @ (posedge clk)
    cntr<=cntr+SW0;
    if (Q== 49999999)
        begin
            cntr<=cntr+2;
            Q<=0;
        end
    else
        Q<=Q+1;
LED<=cntr;
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module v_5_5(
    input clk,
    input SW1,
    input SW2,
    output reg [7:4] LED
    );
    reg [25:0] Q;
    reg [3:0] shr=4'b0001;
    always @ (posedge clk)
    begin
        if(SW1==0)
            shr<=4'b0001;
        else
            if(Q==49999999)
                begin
                    Q<=0;
                    if(SW2)
                        shr<={shr[0],shr[3:1]};
                    else
                        shr<={shr[2:0],shr[3]};
                end
            else
                Q<=Q+1;
    LED<=shr;
    end
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module v_5_6(
    input clk,
    input BTN0,
    output reg [7:0] LED);
    reg [25:0] Q =0;
    reg [7:0] shr=8'b00000001;
    reg dir=0// 0-balra|1-jobb
    always @ (posedge clk)
        begin
        if(BTN0)
            shr<=8'b00000001;
        else
            if(Q==49999999)
                begin
                    if(shr[7]) dir<=1;if(shr[0]) dir<=0;
                    if (dir)
                        shr<={shr[0],shr[7:1]};
                    else
                        shr<={shr[6:0],shr[7]};
                end
            else
                Q<=Q+1;
        LED<=shr;
        end
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module v_5_7(
    input clk,
    input SW0;
    output LD0;
    );
    reg [25:0] Q;
    reg d=1;
    always @ (posedge clk)
        if( Q==49999999)
            begin
                if(SW0)
                    d=~d;
                else
                    d=1;
            end
        else
            Q<=Q+1;
        LD0<=d;
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module v_5_8(
    input clk,
    output reg [6:0] SEG,
    output reg [3:0] AN);
    reg[25:0] mp =0;
    reg [10:0] khz =0;
    reg[3:0] shr=4'b1110;
    reg[3:0] shr2=4'b1110;
    always @ (posedge clk)
        begin
            if(mp_en)
                mp<=0;
            else
                mp<=mp+1;
        end
    assign mp_en=(mp==20);
    always @ (posedge clk)
        begin
            if(khz_en)
                khz<=0;
            else
                khz<=khz+1;
        end
    assign khz_en=(khz==5);
    always @ (posedge clk)
        begin
            if(khz_en)
                shr<={shr[2:0],shr[3]};
            else
                shr<=shr;
        AN<=shr;
        end
    always @ (posedge clk)
        begin
            if(mp_en)
                shr2<={shr[2:0],shr[3]};
            else
                shr2<=shr2;
        end
    always @ (posedge clk)
        if(shr2==shr) SEG<=7'b0111111; else SEG<=7'b0000000;
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module v_5_9(
    input clk,
    input SW0,
    output reg[6:0] SEG,
    output reg[3:0] AN,
    output LED0,
    output LED1);
    reg [25:0] Q =0;
    reg [3:0] cnt=0;
    reg [3:0] cntr=0;
    assign AN<=4'b1110;
    always @(posedge clk)
        if(Q==49999999)
            begin
            if(SW0)
                begin
                if(cnt==9) cnt<=0;
                cnt<=cnt+1;
                end
            else
                begin
                if(cnt==0) cnt<=9;
                cnt<=cnt-1;
                end
            end
        else
            Q<=Q+1;
        if(Q==1000) cntr<=cnt;
   always @(cntr)
      case (cntr)
          4'b0001 : SEG = 7'b1111001;   // 1
          4'b0010 : SEG = 7'b0100100;   // 2
          4'b0011 : SEG = 7'b0110000;   // 3
          4'b0100 : SEG = 7'b0011001;   // 4
          4'b0101 : SEG = 7'b0010010;   // 5
          4'b0110 : SEG = 7'b0000010;   // 6
          4'b0111 : SEG = 7'b1111000;   // 7
          4'b1000 : SEG = 7'b0000000;   // 8
          4'b1001 : SEG = 7'b0010000;   // 9
          default : SEG = 7'b1000000;   // 0
      endcase
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////