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-- Company:
-- Engineer:
--
-- Create Date: 10/23/2019 04:15:52 PM
-- Design Name:
-- Module Name: rippleCarryAdder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rippleCarryAdder is
GENERIC (N : INTEGER:=4);
  Port (  A : in STD_LOGIC_VECTOR(N-1 downto 0);
           B : in STD_LOGIC_VECTOR(N-1 downto 0);
           Cin : in STD_LOGIC;
           S : out STD_LOGIC_VECTOR(N-1 downto 0);
           Cout : out STD_LOGIC);
end rippleCarryAdder;

architecture Behavioral of rippleCarryAdder is

signal carry_out: std_logic_vector(N downto 0);

component fullAdder1 iS
    GENERIC(N : INTEGER);
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Cin : in STD_LOGIC;
           S : out STD_LOGIC;
           Cout : out STD_LOGIC);
end component;

begin
fullA: FOR k IN N-1 downto 0 GENERATE
ca: fullAdder1
GENERIC MAP( N => 4)
 port map ( A(K), B(K),carry_out(k), s(k), carry_out(k+1));
end GENERATE fullA;

carry_out(0) <= cin;
cout <= carry_out(N);

end Behavioral;