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  1. Disassembly of section .text:
  2.  
  3. 080000b8 <__ctzsi2>:
  4. 80000b8: 4241 negs r1, r0
  5. 80000ba: 4008 ands r0, r1
  6. 80000bc: 211c movs r1, #28
  7. 80000be: 2301 movs r3, #1
  8. 80000c0: 041b lsls r3, r3, #16
  9. 80000c2: 4298 cmp r0, r3
  10. 80000c4: d301 bcc.n 80000ca <__ctzsi2+0x12>
  11. 80000c6: 0c00 lsrs r0, r0, #16
  12. 80000c8: 3910 subs r1, #16
  13. 80000ca: 0a1b lsrs r3, r3, #8
  14. 80000cc: 4298 cmp r0, r3
  15. 80000ce: d301 bcc.n 80000d4 <__ctzsi2+0x1c>
  16. 80000d0: 0a00 lsrs r0, r0, #8
  17. 80000d2: 3908 subs r1, #8
  18. 80000d4: 091b lsrs r3, r3, #4
  19. 80000d6: 4298 cmp r0, r3
  20. 80000d8: d301 bcc.n 80000de <__ctzsi2+0x26>
  21. 80000da: 0900 lsrs r0, r0, #4
  22. 80000dc: 3904 subs r1, #4
  23. 80000de: a202 add r2, pc, #8 @ (adr r2, 80000e8 <__ctzsi2+0x30>)
  24. 80000e0: 5c10 ldrb r0, [r2, r0]
  25. 80000e2: 1a40 subs r0, r0, r1
  26. 80000e4: 4770 bx lr
  27. 80000e6: 46c0 nop @ (mov r8, r8)
  28. 80000e8: 1d1d1c1b .word 0x1d1d1c1b
  29. 80000ec: 1e1e1e1e .word 0x1e1e1e1e
  30. 80000f0: 1f1f1f1f .word 0x1f1f1f1f
  31. 80000f4: 1f1f1f1f .word 0x1f1f1f1f
  32.  
  33. 080000f8 <deregister_tm_clones>:
  34. 80000f8: 4804 ldr r0, [pc, #16] @ (800010c <deregister_tm_clones+0x14>)
  35. 80000fa: 4b05 ldr r3, [pc, #20] @ (8000110 <deregister_tm_clones+0x18>)
  36. 80000fc: b510 push {r4, lr}
  37. 80000fe: 4283 cmp r3, r0
  38. 8000100: d003 beq.n 800010a <deregister_tm_clones+0x12>
  39. 8000102: 4b04 ldr r3, [pc, #16] @ (8000114 <deregister_tm_clones+0x1c>)
  40. 8000104: 2b00 cmp r3, #0
  41. 8000106: d000 beq.n 800010a <deregister_tm_clones+0x12>
  42. 8000108: 4798 blx r3
  43. 800010a: bd10 pop {r4, pc}
  44. 800010c: 20000004 .word 0x20000004
  45. 8000110: 20000004 .word 0x20000004
  46. 8000114: 00000000 .word 0x00000000
  47.  
  48. 08000118 <register_tm_clones>:
  49. 8000118: 4806 ldr r0, [pc, #24] @ (8000134 <register_tm_clones+0x1c>)
  50. 800011a: 4907 ldr r1, [pc, #28] @ (8000138 <register_tm_clones+0x20>)
  51. 800011c: 1a09 subs r1, r1, r0
  52. 800011e: 108b asrs r3, r1, #2
  53. 8000120: 0fc9 lsrs r1, r1, #31
  54. 8000122: 18c9 adds r1, r1, r3
  55. 8000124: b510 push {r4, lr}
  56. 8000126: 1049 asrs r1, r1, #1
  57. 8000128: d003 beq.n 8000132 <register_tm_clones+0x1a>
  58. 800012a: 4b04 ldr r3, [pc, #16] @ (800013c <register_tm_clones+0x24>)
  59. 800012c: 2b00 cmp r3, #0
  60. 800012e: d000 beq.n 8000132 <register_tm_clones+0x1a>
  61. 8000130: 4798 blx r3
  62. 8000132: bd10 pop {r4, pc}
  63. 8000134: 20000004 .word 0x20000004
  64. 8000138: 20000004 .word 0x20000004
  65. 800013c: 00000000 .word 0x00000000
  66.  
  67. 08000140 <__do_global_dtors_aux>:
  68. 8000140: b510 push {r4, lr}
  69. 8000142: 4c07 ldr r4, [pc, #28] @ (8000160 <__do_global_dtors_aux+0x20>)
  70. 8000144: 7823 ldrb r3, [r4, #0]
  71. 8000146: 2b00 cmp r3, #0
  72. 8000148: d109 bne.n 800015e <__do_global_dtors_aux+0x1e>
  73. 800014a: f7ff ffd5 bl 80000f8 <deregister_tm_clones>
  74. 800014e: 4b05 ldr r3, [pc, #20] @ (8000164 <__do_global_dtors_aux+0x24>)
  75. 8000150: 2b00 cmp r3, #0
  76. 8000152: d002 beq.n 800015a <__do_global_dtors_aux+0x1a>
  77. 8000154: 4804 ldr r0, [pc, #16] @ (8000168 <__do_global_dtors_aux+0x28>)
  78. 8000156: e000 b.n 800015a <__do_global_dtors_aux+0x1a>
  79. 8000158: bf00 nop
  80. 800015a: 2301 movs r3, #1
  81. 800015c: 7023 strb r3, [r4, #0]
  82. 800015e: bd10 pop {r4, pc}
  83. 8000160: 20000004 .word 0x20000004
  84. 8000164: 00000000 .word 0x00000000
  85. 8000168: 08000b48 .word 0x08000b48
  86.  
  87. 0800016c <frame_dummy>:
  88. 800016c: 4b05 ldr r3, [pc, #20] @ (8000184 <frame_dummy+0x18>)
  89. 800016e: b510 push {r4, lr}
  90. 8000170: 2b00 cmp r3, #0
  91. 8000172: d003 beq.n 800017c <frame_dummy+0x10>
  92. 8000174: 4904 ldr r1, [pc, #16] @ (8000188 <frame_dummy+0x1c>)
  93. 8000176: 4805 ldr r0, [pc, #20] @ (800018c <frame_dummy+0x20>)
  94. 8000178: e000 b.n 800017c <frame_dummy+0x10>
  95. 800017a: bf00 nop
  96. 800017c: f7ff ffcc bl 8000118 <register_tm_clones>
  97. 8000180: bd10 pop {r4, pc}
  98. 8000182: 46c0 nop @ (mov r8, r8)
  99. 8000184: 00000000 .word 0x00000000
  100. 8000188: 20000008 .word 0x20000008
  101. 800018c: 08000b48 .word 0x08000b48
  102.  
  103. 08000190 <(anonymous namespace)::HandleButtonPress(mcu::stm32g070::Gpio::GpioId)>:
  104. #include "platform/mcu-hal/gpio.hpp"
  105.  
  106. namespace {
  107. bool button_pressed = false;
  108. void HandleButtonPress([[maybe_unused]] GpioId pin) {
  109. button_pressed = true;
  110. 8000190: 4b01 ldr r3, [pc, #4] @ (8000198 <(anonymous namespace)::HandleButtonPress(mcu::stm32g070::Gpio::GpioId)+0x8>)
  111. 8000192: 2201 movs r2, #1
  112. 8000194: 701a strb r2, [r3, #0]
  113. }
  114. 8000196: 4770 bx lr
  115. 8000198: 20000020 .word 0x20000020
  116.  
  117. 0800019c <void rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>::FunctionStub<&(anonymous namespace)::HandleButtonPress>(void*, mcu::stm32g070::Gpio::GpioId)>:
  118. using StubType = ReturnType (*)(void*, Args...);
  119. void* object_ptr = nullptr;
  120. StubType stub_ptr = nullptr;
  121.  
  122. template <ReturnType (*Function)(Args...)>
  123. static ReturnType FunctionStub(void*, Args... args) {
  124. 800019c: b510 push {r4, lr}
  125. 800019e: 0008 movs r0, r1
  126. return Function(std::forward<Args>(args)...);
  127. 80001a0: f7ff fff6 bl 8000190 <(anonymous namespace)::HandleButtonPress(mcu::stm32g070::Gpio::GpioId)>
  128. }
  129. 80001a4: bd10 pop {r4, pc}
  130.  
  131. 080001a6 <mcu::hal::Uart<mcu::stm32g070::Uart>::Transmit(char const*)>:
  132.  
  133. void Transmit(const uint8_t *data, size_t len) {
  134. impl_.Transmit(data, len);
  135. }
  136.  
  137. void Transmit(const char *str) {
  138. 80001a6: b570 push {r4, r5, r6, lr}
  139. 80001a8: 0005 movs r5, r0
  140. 80001aa: 000c movs r4, r1
  141. while (*str != '\0') {
  142. 80001ac: e005 b.n 80001ba <mcu::hal::Uart<mcu::stm32g070::Uart>::Transmit(char const*)+0x14>
  143. impl_.Transmit(reinterpret_cast<const uint8_t *>(str), 1);
  144. 80001ae: 2201 movs r2, #1
  145. 80001b0: 0021 movs r1, r4
  146. 80001b2: 0028 movs r0, r5
  147. 80001b4: f000 fbe7 bl 8000986 <mcu::stm32g070::Uart::Transmit(unsigned char const*, unsigned int)>
  148. str++;
  149. 80001b8: 3401 adds r4, #1
  150. while (*str != '\0') {
  151. 80001ba: 7823 ldrb r3, [r4, #0]
  152. 80001bc: 2b00 cmp r3, #0
  153. 80001be: d1f6 bne.n 80001ae <mcu::hal::Uart<mcu::stm32g070::Uart>::Transmit(char const*)+0x8>
  154. }
  155. }
  156. 80001c0: bd70 pop {r4, r5, r6, pc}
  157. ...
  158.  
  159. 080001c4 <main>:
  160. } // namespace
  161.  
  162. extern "C" int main(void) {
  163. 80001c4: b530 push {r4, r5, lr}
  164. 80001c6: b087 sub sp, #28
  165. Board::Init();
  166. 80001c8: f000 f85c bl 8000284 <Board::Init()>
  167. LogicLevel Read() {
  168. return Impl::Read(pinId);
  169. }
  170.  
  171. void Write(LogicLevel value) {
  172. Impl::Write(pinId, value);
  173. 80001cc: 2100 movs r1, #0
  174. 80001ce: 2005 movs r0, #5
  175. 80001d0: f000 f9ed bl 80005ae <mcu::stm32g070::Gpio::Write(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::LogicLevel)>
  176. bool operator!=(const Delegate& other) const {
  177. return !(*this == other);
  178. }
  179.  
  180. private:
  181. Delegate(void* object, StubType stub) : object_ptr(object), stub_ptr(stub) {
  182. 80001d4: 2200 movs r2, #0
  183. 80001d6: 9200 str r2, [sp, #0]
  184. 80001d8: 4b16 ldr r3, [pc, #88] @ (8000234 <main+0x70>)
  185. 80001da: 9301 str r3, [sp, #4]
  186. : object_ptr(other.object_ptr), stub_ptr(other.stub_ptr) {
  187. 80001dc: 9202 str r2, [sp, #8]
  188. 80001de: 9303 str r3, [sp, #12]
  189. 80001e0: 9204 str r2, [sp, #16]
  190. 80001e2: 9305 str r3, [sp, #20]
  191. Impl::Toggle(pinId);
  192. }
  193.  
  194. void ConfigureInterrupt(InterruptEvent interrupt_mode,
  195. InterruptDelegate callback) {
  196. Impl::ConfigureInterrupt(pinId, interrupt_mode, callback);
  197. 80001e4: aa04 add r2, sp, #16
  198. 80001e6: 2101 movs r1, #1
  199. 80001e8: 202d movs r0, #45 @ 0x2d
  200. 80001ea: f000 fa09 bl 8000600 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)>
  201. IOPin<BoardPin::kButton> button;
  202. auto button_handler = GpioInterruptFunc::Create<HandleButtonPress>();
  203. button.ConfigureInterrupt(mcu::hal::gpio::InterruptEvent::kFallingEdge,
  204. button_handler);
  205.  
  206. auto &console_uart = Board::ConsoleUart();
  207. 80001ee: f000 f86f bl 80002d0 <Board::ConsoleUart()>
  208. 80001f2: 0005 movs r5, r0
  209. impl_.Enable();
  210. 80001f4: f000 fbb8 bl 8000968 <mcu::stm32g070::Uart::Enable()>
  211. console_uart.Enable();
  212. console_uart.Transmit("Board Init Complete\n");
  213. 80001f8: 490f ldr r1, [pc, #60] @ (8000238 <main+0x74>)
  214. 80001fa: 0028 movs r0, r5
  215. 80001fc: f7ff ffd3 bl 80001a6 <mcu::hal::Uart<mcu::stm32g070::Uart>::Transmit(char const*)>
  216.  
  217. uint32_t counter = 0;
  218. 8000200: 2400 movs r4, #0
  219. while (true) {
  220. if (counter == 0x1ffff0) {
  221. 8000202: 4b0e ldr r3, [pc, #56] @ (800023c <main+0x78>)
  222. 8000204: 429c cmp r4, r3
  223. 8000206: d00c beq.n 8000222 <main+0x5e>
  224. led.Toggle();
  225. counter = 0;
  226. console_uart.Transmit("Hello World!\n");
  227. }
  228. counter++;
  229. 8000208: 3401 adds r4, #1
  230.  
  231. if (button_pressed) {
  232. 800020a: 4b0d ldr r3, [pc, #52] @ (8000240 <main+0x7c>)
  233. 800020c: 781b ldrb r3, [r3, #0]
  234. 800020e: 2b00 cmp r3, #0
  235. 8000210: d0f7 beq.n 8000202 <main+0x3e>
  236. console_uart.Transmit("Button pressed\n");
  237. 8000212: 490c ldr r1, [pc, #48] @ (8000244 <main+0x80>)
  238. 8000214: 0028 movs r0, r5
  239. 8000216: f7ff ffc6 bl 80001a6 <mcu::hal::Uart<mcu::stm32g070::Uart>::Transmit(char const*)>
  240. button_pressed = false;
  241. 800021a: 4b09 ldr r3, [pc, #36] @ (8000240 <main+0x7c>)
  242. 800021c: 2200 movs r2, #0
  243. 800021e: 701a strb r2, [r3, #0]
  244. 8000220: e7ef b.n 8000202 <main+0x3e>
  245. Impl::Toggle(pinId);
  246. 8000222: 2005 movs r0, #5
  247. 8000224: f000 f9d6 bl 80005d4 <mcu::stm32g070::Gpio::Toggle(mcu::stm32g070::Gpio::GpioId)>
  248. console_uart.Transmit("Hello World!\n");
  249. 8000228: 4907 ldr r1, [pc, #28] @ (8000248 <main+0x84>)
  250. 800022a: 0028 movs r0, r5
  251. 800022c: f7ff ffbb bl 80001a6 <mcu::hal::Uart<mcu::stm32g070::Uart>::Transmit(char const*)>
  252. counter = 0;
  253. 8000230: 2400 movs r4, #0
  254. 8000232: e7e9 b.n 8000208 <main+0x44>
  255. 8000234: 0800019d .word 0x0800019d
  256. 8000238: 08000b60 .word 0x08000b60
  257. 800023c: 001ffff0 .word 0x001ffff0
  258. 8000240: 20000020 .word 0x20000020
  259. 8000244: 08000b88 .word 0x08000b88
  260. 8000248: 08000b78 .word 0x08000b78
  261.  
  262. 0800024c <__assert_func>:
  263.  
  264. __attribute__((noreturn)) void __assert_func(
  265. [[maybe_unused]] const char* file, [[maybe_unused]] int line,
  266. [[maybe_unused]] const char* func,
  267. [[maybe_unused]] const char* failedexpr) {
  268. while (1) {
  269. 800024c: e7fe b.n 800024c <__assert_func>
  270. ...
  271.  
  272. 08000250 <Board::Board()>:
  273. .rx_pin = static_cast<GpioId>(BoardPin::kConsoleUartRx),
  274. .baud_rate = BaudRate::k115200,
  275. };
  276. } // namespace
  277.  
  278. Board::Board()
  279. 8000250: b530 push {r4, r5, lr}
  280. 8000252: b083 sub sp, #12
  281. 8000254: 0004 movs r4, r0
  282. template<contiguous_iterator _It>
  283. requires __is_compatible_ref<iter_reference_t<_It>>::value
  284. constexpr explicit(extent != dynamic_extent)
  285. span(_It __first, size_type __count)
  286. noexcept
  287. : _M_ptr(std::to_address(__first)), _M_extent(__count)
  288. 8000256: 4b09 ldr r3, [pc, #36] @ (800027c <Board::Board()+0x2c>)
  289. 8000258: 6003 str r3, [r0, #0]
  290. : _M_extent_value(__extent)
  291. 800025a: 2304 movs r3, #4
  292. 800025c: 6043 str r3, [r0, #4]
  293. 800025e: 466b mov r3, sp
  294. 8000260: c822 ldmia r0!, {r1, r5}
  295. 8000262: c322 stmia r3!, {r1, r5}
  296. : impl_(default_pin_configurations) {
  297. 8000264: 9900 ldr r1, [sp, #0]
  298. 8000266: 2204 movs r2, #4
  299. 8000268: f000 f922 bl 80004b0 <mcu::stm32g070::Gpio::Gpio(std::span<mcu::stm32g070::Gpio::GpioConfig const, 4294967295u>)>
  300. Uart(UartConfig const &uart_config) : impl_(uart_config) {
  301. 800026c: 4904 ldr r1, [pc, #16] @ (8000280 <Board::Board()+0x30>)
  302. 800026e: 0020 movs r0, r4
  303. 8000270: 3010 adds r0, #16
  304. 8000272: f000 fb49 bl 8000908 <mcu::stm32g070::Uart::Uart(mcu::stm32g070::Uart::UartConfig const&)>
  305. : gpio_config_{gpio_config},
  306. gpio_(gpio_config_),
  307. console_uart_(console_uart) {
  308. }
  309. 8000276: 0020 movs r0, r4
  310. 8000278: b003 add sp, #12
  311. 800027a: bd30 pop {r4, r5, pc}
  312. 800027c: 08001110 .word 0x08001110
  313. 8000280: 08001108 .word 0x08001108
  314.  
  315. 08000284 <Board::Init()>:
  316.  
  317. void Board::Init() {
  318. 8000284: b570 push {r4, r5, r6, lr}
  319. mcu::stm32g070::SysClock::Init();
  320. 8000286: f000 fae5 bl 8000854 <mcu::stm32g070::SysClock::Init()>
  321. assert(instance_ptr == nullptr);
  322. 800028a: 4b0c ldr r3, [pc, #48] @ (80002bc <Board::Init()+0x38>)
  323. 800028c: 681b ldr r3, [r3, #0]
  324. 800028e: 2b00 cmp r3, #0
  325. 8000290: d10e bne.n 80002b0 <Board::Init()+0x2c>
  326. instance_ptr = new (board_object_storage) Board();
  327. 8000292: 4c0b ldr r4, [pc, #44] @ (80002c0 <Board::Init()+0x3c>)
  328. 8000294: 0020 movs r0, r4
  329. 8000296: f7ff ffdb bl 8000250 <Board::Board()>
  330. 800029a: 4d08 ldr r5, [pc, #32] @ (80002bc <Board::Init()+0x38>)
  331. 800029c: 602c str r4, [r5, #0]
  332. impl_.ConfigureAllToDefault();
  333. 800029e: 0020 movs r0, r4
  334. 80002a0: 3008 adds r0, #8
  335. 80002a2: f000 f973 bl 800058c <mcu::stm32g070::Gpio::ConfigureAllToDefault()>
  336. instance_ptr->gpio_.ConfigureAllToDefault();
  337. instance_ptr->console_uart_.Init();
  338. 80002a6: 6828 ldr r0, [r5, #0]
  339. impl_.Init();
  340. 80002a8: 3010 adds r0, #16
  341. 80002aa: f000 fb35 bl 8000918 <mcu::stm32g070::Uart::Init()>
  342. }
  343. 80002ae: bd70 pop {r4, r5, r6, pc}
  344. assert(instance_ptr == nullptr);
  345. 80002b0: 4b04 ldr r3, [pc, #16] @ (80002c4 <Board::Init()+0x40>)
  346. 80002b2: 4a05 ldr r2, [pc, #20] @ (80002c8 <Board::Init()+0x44>)
  347. 80002b4: 4805 ldr r0, [pc, #20] @ (80002cc <Board::Init()+0x48>)
  348. 80002b6: 2146 movs r1, #70 @ 0x46
  349. 80002b8: f7ff ffc8 bl 800024c <__assert_func>
  350. 80002bc: 20000024 .word 0x20000024
  351. 80002c0: 20000028 .word 0x20000028
  352. 80002c4: 08000b98 .word 0x08000b98
  353. 80002c8: 08000bb0 .word 0x08000bb0
  354. 80002cc: 08000bcc .word 0x08000bcc
  355.  
  356. 080002d0 <Board::ConsoleUart()>:
  357. mcu::hal::Gpio<mcu::stm32g070::Gpio> &Board::Gpio() {
  358. assert(instance_ptr != nullptr);
  359. return instance_ptr->gpio_;
  360. }
  361.  
  362. mcu::hal::Uart<mcu::stm32g070::Uart> &Board::ConsoleUart() {
  363. 80002d0: b510 push {r4, lr}
  364. assert(instance_ptr != nullptr);
  365. 80002d2: 4b06 ldr r3, [pc, #24] @ (80002ec <Board::ConsoleUart()+0x1c>)
  366. 80002d4: 6818 ldr r0, [r3, #0]
  367. 80002d6: 2800 cmp r0, #0
  368. 80002d8: d001 beq.n 80002de <Board::ConsoleUart()+0xe>
  369. return instance_ptr->console_uart_;
  370. 80002da: 3010 adds r0, #16
  371. }
  372. 80002dc: bd10 pop {r4, pc}
  373. assert(instance_ptr != nullptr);
  374. 80002de: 4b04 ldr r3, [pc, #16] @ (80002f0 <Board::ConsoleUart()+0x20>)
  375. 80002e0: 4a04 ldr r2, [pc, #16] @ (80002f4 <Board::ConsoleUart()+0x24>)
  376. 80002e2: 4805 ldr r0, [pc, #20] @ (80002f8 <Board::ConsoleUart()+0x28>)
  377. 80002e4: 2152 movs r1, #82 @ 0x52
  378. 80002e6: f7ff ffb1 bl 800024c <__assert_func>
  379. 80002ea: 46c0 nop @ (mov r8, r8)
  380. 80002ec: 20000024 .word 0x20000024
  381. 80002f0: 08000be8 .word 0x08000be8
  382. 80002f4: 08000c3c .word 0x08000c3c
  383. 80002f8: 08000bcc .word 0x08000bcc
  384.  
  385. 080002fc <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)>:
  386. };
  387.  
  388. std::array<GpioInterruptInfo, 16> irq_callback_table{};
  389.  
  390. GPIO_TypeDef *GetPortRegister(mcu::stm32g070::Gpio::GpioId pin) {
  391. uint8_t port_num = pin >> kNumPinsPerPortShift;
  392. 80002fc: 0903 lsrs r3, r0, #4
  393. switch (port_num) {
  394. 80002fe: 284f cmp r0, #79 @ 0x4f
  395. 8000300: d80c bhi.n 800031c <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x20>
  396. 8000302: 009b lsls r3, r3, #2
  397. 8000304: 4a07 ldr r2, [pc, #28] @ (8000324 <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x28>)
  398. 8000306: 58d3 ldr r3, [r2, r3]
  399. 8000308: 469f mov pc, r3
  400. 800030a: 20a0 movs r0, #160 @ 0xa0
  401. 800030c: 05c0 lsls r0, r0, #23
  402. case 4:
  403. return GPIOF;
  404. default:
  405. return nullptr;
  406. }
  407. }
  408. 800030e: 4770 bx lr
  409. return GPIOC;
  410. 8000310: 4805 ldr r0, [pc, #20] @ (8000328 <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x2c>)
  411. 8000312: e7fc b.n 800030e <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x12>
  412. return GPIOD;
  413. 8000314: 4805 ldr r0, [pc, #20] @ (800032c <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x30>)
  414. 8000316: e7fa b.n 800030e <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x12>
  415. return GPIOF;
  416. 8000318: 4805 ldr r0, [pc, #20] @ (8000330 <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x34>)
  417. 800031a: e7f8 b.n 800030e <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x12>
  418. return nullptr;
  419. 800031c: 2000 movs r0, #0
  420. 800031e: e7f6 b.n 800030e <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x12>
  421. return GPIOB;
  422. 8000320: 4804 ldr r0, [pc, #16] @ (8000334 <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x38>)
  423. 8000322: e7f4 b.n 800030e <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)+0x12>
  424. 8000324: 08001128 .word 0x08001128
  425. 8000328: 50000800 .word 0x50000800
  426. 800032c: 50000c00 .word 0x50000c00
  427. 8000330: 50001400 .word 0x50001400
  428. 8000334: 50000400 .word 0x50000400
  429.  
  430. 08000338 <(anonymous namespace)::SetPullResistor(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioPullResistor)>:
  431.  
  432. void SetPullResistor(GPIO_TypeDef *port, uint8_t port_pin,
  433. mcu::stm32g070::Gpio::GpioPullResistor mode) {
  434. 8000338: b510 push {r4, lr}
  435. uint8_t bit_value = (mode == mcu::stm32g070::Gpio::kPullNone) ? 0b00
  436. 800033a: 2a02 cmp r2, #2
  437. 800033c: d003 beq.n 8000346 <(anonymous namespace)::SetPullResistor(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioPullResistor)+0xe>
  438. 800033e: 2a00 cmp r2, #0
  439. 8000340: d110 bne.n 8000364 <(anonymous namespace)::SetPullResistor(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioPullResistor)+0x2c>
  440. 8000342: 3201 adds r2, #1
  441. 8000344: e000 b.n 8000348 <(anonymous namespace)::SetPullResistor(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioPullResistor)+0x10>
  442. 8000346: 2200 movs r2, #0
  443. : (mode == mcu::stm32g070::Gpio::kPullUp)
  444. ? 0b01
  445. : 0b10; // pull-down
  446. port->PUPDR &= ~(0b11 << (port_pin < 1));
  447. 8000348: 68c4 ldr r4, [r0, #12]
  448. 800034a: 2900 cmp r1, #0
  449. 800034c: d10c bne.n 8000368 <(anonymous namespace)::SetPullResistor(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioPullResistor)+0x30>
  450. 800034e: 2307 movs r3, #7
  451. 8000350: 425b negs r3, r3
  452. 8000352: 4023 ands r3, r4
  453. 8000354: 60c3 str r3, [r0, #12]
  454. port->PUPDR |= bit_value << (port_pin < 1);
  455. 8000356: 68c3 ldr r3, [r0, #12]
  456. 8000358: 424c negs r4, r1
  457. 800035a: 4161 adcs r1, r4
  458. 800035c: 408a lsls r2, r1
  459. 800035e: 4313 orrs r3, r2
  460. 8000360: 60c3 str r3, [r0, #12]
  461. }
  462. 8000362: bd10 pop {r4, pc}
  463. uint8_t bit_value = (mode == mcu::stm32g070::Gpio::kPullNone) ? 0b00
  464. 8000364: 2202 movs r2, #2
  465. 8000366: e7ef b.n 8000348 <(anonymous namespace)::SetPullResistor(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioPullResistor)+0x10>
  466. port->PUPDR &= ~(0b11 << (port_pin < 1));
  467. 8000368: 2304 movs r3, #4
  468. 800036a: 425b negs r3, r3
  469. 800036c: e7f1 b.n 8000352 <(anonymous namespace)::SetPullResistor(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioPullResistor)+0x1a>
  470.  
  471. 0800036e <(anonymous namespace)::SetOutputConfig(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioOutputType, mcu::stm32g070::Gpio::GpioOutputSpeed)>:
  472.  
  473. void SetOutputConfig(GPIO_TypeDef *port, uint8_t port_pin,
  474. mcu::stm32g070::Gpio::GpioOutputType output_type,
  475. mcu::stm32g070::Gpio::GpioOutputSpeed speed) {
  476. 800036e: b510 push {r4, lr}
  477. 8000370: 001c movs r4, r3
  478. if (output_type == mcu::stm32g070::Gpio::kPushPull) {
  479. 8000372: 2a00 cmp r2, #0
  480. 8000374: d10e bne.n 8000394 <(anonymous namespace)::SetOutputConfig(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioOutputType, mcu::stm32g070::Gpio::GpioOutputSpeed)+0x26>
  481. port->OTYPER &= ~(0b1 << port_pin);
  482. 8000376: 6843 ldr r3, [r0, #4]
  483. 8000378: 3201 adds r2, #1
  484. 800037a: 408a lsls r2, r1
  485. 800037c: 4393 bics r3, r2
  486. 800037e: 6043 str r3, [r0, #4]
  487. } else {
  488. port->OTYPER |= 0b1 << port_pin;
  489. }
  490. port->OSPEEDR &= ~(0b11 << port_pin);
  491. 8000380: 6883 ldr r3, [r0, #8]
  492. 8000382: 2203 movs r2, #3
  493. 8000384: 408a lsls r2, r1
  494. 8000386: 4393 bics r3, r2
  495. 8000388: 6083 str r3, [r0, #8]
  496. port->OSPEEDR |= speed << port_pin;
  497. 800038a: 6883 ldr r3, [r0, #8]
  498. 800038c: 408c lsls r4, r1
  499. 800038e: 4323 orrs r3, r4
  500. 8000390: 6083 str r3, [r0, #8]
  501. }
  502. 8000392: bd10 pop {r4, pc}
  503. port->OTYPER |= 0b1 << port_pin;
  504. 8000394: 6843 ldr r3, [r0, #4]
  505. 8000396: 2201 movs r2, #1
  506. 8000398: 408a lsls r2, r1
  507. 800039a: 4313 orrs r3, r2
  508. 800039c: 6043 str r3, [r0, #4]
  509. 800039e: e7ef b.n 8000380 <(anonymous namespace)::SetOutputConfig(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioOutputType, mcu::stm32g070::Gpio::GpioOutputSpeed)+0x12>
  510.  
  511. 080003a0 <(anonymous namespace)::SetAltConfig(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioAltFunc)>:
  512.  
  513. void SetAltConfig(GPIO_TypeDef *port, uint8_t port_pin,
  514. mcu::stm32g070::Gpio::GpioAltFunc af) {
  515. 80003a0: b530 push {r4, r5, lr}
  516. uint8_t low_hi_sel = port_pin >> 3;
  517. 80003a2: 08cb lsrs r3, r1, #3
  518. uint8_t af_pin_shift = (port_pin & 0x7) << 2;
  519. 80003a4: 0089 lsls r1, r1, #2
  520. 80003a6: 241c movs r4, #28
  521. 80003a8: 4021 ands r1, r4
  522. port->AFR[low_hi_sel] &= ~(0xf << af_pin_shift);
  523. 80003aa: 3308 adds r3, #8
  524. 80003ac: 009b lsls r3, r3, #2
  525. 80003ae: 581c ldr r4, [r3, r0]
  526. 80003b0: 250f movs r5, #15
  527. 80003b2: 408d lsls r5, r1
  528. 80003b4: 43ac bics r4, r5
  529. 80003b6: 501c str r4, [r3, r0]
  530. port->AFR[low_hi_sel] |= (af << af_pin_shift);
  531. 80003b8: 581c ldr r4, [r3, r0]
  532. 80003ba: 408a lsls r2, r1
  533. 80003bc: 4314 orrs r4, r2
  534. 80003be: 501c str r4, [r3, r0]
  535. }
  536. 80003c0: bd30 pop {r4, r5, pc}
  537. ...
  538.  
  539. 080003c4 <(anonymous namespace)::EnablePortClockIfFirstUse((anonymous namespace)::GpioPortId)>:
  540.  
  541. GpioPortRefCounter io_port_ref_counters[kNumPorts];
  542.  
  543. void EnablePortClockIfFirstUse(GpioPortId port_id) {
  544. GpioPortRefCounter *ref_counter = &io_port_ref_counters[port_id];
  545. uint8_t ref_count = ref_counter->gpio_ref_count + ref_counter->adc_ref_count;
  546. 80003c4: 4b08 ldr r3, [pc, #32] @ (80003e8 <(anonymous namespace)::EnablePortClockIfFirstUse((anonymous namespace)::GpioPortId)+0x24>)
  547. 80003c6: 0041 lsls r1, r0, #1
  548. 80003c8: 5cca ldrb r2, [r1, r3]
  549. 80003ca: 185b adds r3, r3, r1
  550. 80003cc: 785b ldrb r3, [r3, #1]
  551. 80003ce: 18d3 adds r3, r2, r3
  552. 80003d0: b2db uxtb r3, r3
  553. if (ref_count == 1) {
  554. 80003d2: 2b01 cmp r3, #1
  555. 80003d4: d000 beq.n 80003d8 <(anonymous namespace)::EnablePortClockIfFirstUse((anonymous namespace)::GpioPortId)+0x14>
  556. // First instance of IO port usage, enable RCC IO port clock
  557. uint32_t mask = 0b1 << port_id;
  558. RCC->IOPENR |= mask;
  559. }
  560. }
  561. 80003d6: 4770 bx lr
  562. uint32_t mask = 0b1 << port_id;
  563. 80003d8: 2201 movs r2, #1
  564. 80003da: 4082 lsls r2, r0
  565. RCC->IOPENR |= mask;
  566. 80003dc: 4903 ldr r1, [pc, #12] @ (80003ec <(anonymous namespace)::EnablePortClockIfFirstUse((anonymous namespace)::GpioPortId)+0x28>)
  567. 80003de: 6b4b ldr r3, [r1, #52] @ 0x34
  568. 80003e0: 4313 orrs r3, r2
  569. 80003e2: 634b str r3, [r1, #52] @ 0x34
  570. }
  571. 80003e4: e7f7 b.n 80003d6 <(anonymous namespace)::EnablePortClockIfFirstUse((anonymous namespace)::GpioPortId)+0x12>
  572. 80003e6: 46c0 nop @ (mov r8, r8)
  573. 80003e8: 20000050 .word 0x20000050
  574. 80003ec: 40021000 .word 0x40021000
  575.  
  576. 080003f0 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)>:
  577. GpioPortId GetPortIdFromPortRegisters(GPIO_TypeDef *port) {
  578. 80003f0: b510 push {r4, lr}
  579. if (port == GPIOA) {
  580. 80003f2: 23a0 movs r3, #160 @ 0xa0
  581. 80003f4: 05db lsls r3, r3, #23
  582. 80003f6: 4298 cmp r0, r3
  583. 80003f8: d013 beq.n 8000422 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x32>
  584. } else if (port == GPIOB) {
  585. 80003fa: 4b0e ldr r3, [pc, #56] @ (8000434 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x44>)
  586. 80003fc: 4298 cmp r0, r3
  587. 80003fe: d012 beq.n 8000426 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x36>
  588. } else if (port == GPIOC) {
  589. 8000400: 4b0d ldr r3, [pc, #52] @ (8000438 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x48>)
  590. 8000402: 4298 cmp r0, r3
  591. 8000404: d011 beq.n 800042a <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x3a>
  592. } else if (port == GPIOD) {
  593. 8000406: 4b0d ldr r3, [pc, #52] @ (800043c <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x4c>)
  594. 8000408: 4298 cmp r0, r3
  595. 800040a: d010 beq.n 800042e <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x3e>
  596. } else if (port == GPIOF) {
  597. 800040c: 4b0c ldr r3, [pc, #48] @ (8000440 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x50>)
  598. 800040e: 4298 cmp r0, r3
  599. 8000410: d101 bne.n 8000416 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x26>
  600. return kPortF;
  601. 8000412: 2004 movs r0, #4
  602. }
  603. 8000414: bd10 pop {r4, pc}
  604. assert(0);
  605. 8000416: 4b0b ldr r3, [pc, #44] @ (8000444 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x54>)
  606. 8000418: 4a0b ldr r2, [pc, #44] @ (8000448 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x58>)
  607. 800041a: 480c ldr r0, [pc, #48] @ (800044c <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x5c>)
  608. 800041c: 2154 movs r1, #84 @ 0x54
  609. 800041e: f7ff ff15 bl 800024c <__assert_func>
  610. return kPortA;
  611. 8000422: 2000 movs r0, #0
  612. 8000424: e7f6 b.n 8000414 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x24>
  613. return kPortB;
  614. 8000426: 2001 movs r0, #1
  615. 8000428: e7f4 b.n 8000414 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x24>
  616. return kPortC;
  617. 800042a: 2002 movs r0, #2
  618. 800042c: e7f2 b.n 8000414 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x24>
  619. return kPortD;
  620. 800042e: 2003 movs r0, #3
  621. 8000430: e7f0 b.n 8000414 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)+0x24>
  622. 8000432: 46c0 nop @ (mov r8, r8)
  623. 8000434: 50000400 .word 0x50000400
  624. 8000438: 50000800 .word 0x50000800
  625. 800043c: 50000c00 .word 0x50000c00
  626. 8000440: 50001400 .word 0x50001400
  627. 8000444: 08000c80 .word 0x08000c80
  628. 8000448: 08000c84 .word 0x08000c84
  629. 800044c: 08000cd4 .word 0x08000cd4
  630.  
  631. 08000450 <(anonymous namespace)::IncrementPortClockRefCount(GPIO_TypeDef*)>:
  632. if (ref_count == 0) {
  633. // TODO: Disable RCC IO port clock
  634. }
  635. }
  636.  
  637. void IncrementPortClockRefCount(GPIO_TypeDef *port) {
  638. 8000450: b510 push {r4, lr}
  639. GpioPortId port_id = GetPortIdFromPortRegisters(port);
  640. 8000452: f7ff ffcd bl 80003f0 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)>
  641. io_port_ref_counters[port_id].gpio_ref_count++;
  642. 8000456: 4b04 ldr r3, [pc, #16] @ (8000468 <(anonymous namespace)::IncrementPortClockRefCount(GPIO_TypeDef*)+0x18>)
  643. 8000458: 0041 lsls r1, r0, #1
  644. 800045a: 5cca ldrb r2, [r1, r3]
  645. 800045c: 3201 adds r2, #1
  646. 800045e: 54ca strb r2, [r1, r3]
  647. EnablePortClockIfFirstUse(port_id);
  648. 8000460: f7ff ffb0 bl 80003c4 <(anonymous namespace)::EnablePortClockIfFirstUse((anonymous namespace)::GpioPortId)>
  649. }
  650. 8000464: bd10 pop {r4, pc}
  651. 8000466: 46c0 nop @ (mov r8, r8)
  652. 8000468: 20000050 .word 0x20000050
  653.  
  654. 0800046c <(anonymous namespace)::GetPortIdFromPin(mcu::stm32g070::Gpio::GpioId)>:
  655. GpioPortId GetPortIdFromPin(mcu::stm32g070::Gpio::GpioId pin) {
  656. 800046c: b510 push {r4, lr}
  657. return GetPortIdFromPortRegisters(GetPortRegister(pin));
  658. 800046e: f7ff ff45 bl 80002fc <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)>
  659. 8000472: f7ff ffbd bl 80003f0 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)>
  660. }
  661. 8000476: bd10 pop {r4, pc}
  662.  
  663. 08000478 <(anonymous namespace)::DecrementPortClockRefCount(GPIO_TypeDef*)>:
  664.  
  665. void DecrementPortClockRefCount(GPIO_TypeDef *port) {
  666. 8000478: b510 push {r4, lr}
  667. GpioPortId port_id = GetPortIdFromPortRegisters(port);
  668. 800047a: f7ff ffb9 bl 80003f0 <(anonymous namespace)::GetPortIdFromPortRegisters(GPIO_TypeDef*)>
  669. assert(io_port_ref_counters[port_id].gpio_ref_count > 0);
  670. 800047e: 4b08 ldr r3, [pc, #32] @ (80004a0 <(anonymous namespace)::DecrementPortClockRefCount(GPIO_TypeDef*)+0x28>)
  671. 8000480: 0042 lsls r2, r0, #1
  672. 8000482: 5cd3 ldrb r3, [r2, r3]
  673. 8000484: 2b00 cmp r3, #0
  674. 8000486: d004 beq.n 8000492 <(anonymous namespace)::DecrementPortClockRefCount(GPIO_TypeDef*)+0x1a>
  675. io_port_ref_counters[port_id].gpio_ref_count--;
  676. 8000488: 4a05 ldr r2, [pc, #20] @ (80004a0 <(anonymous namespace)::DecrementPortClockRefCount(GPIO_TypeDef*)+0x28>)
  677. 800048a: 0040 lsls r0, r0, #1
  678. 800048c: 3b01 subs r3, #1
  679. 800048e: 5483 strb r3, [r0, r2]
  680. DisablePortClockIfUnused(port_id);
  681. }
  682. 8000490: bd10 pop {r4, pc}
  683. assert(io_port_ref_counters[port_id].gpio_ref_count > 0);
  684. 8000492: 4b04 ldr r3, [pc, #16] @ (80004a4 <(anonymous namespace)::DecrementPortClockRefCount(GPIO_TypeDef*)+0x2c>)
  685. 8000494: 4a04 ldr r2, [pc, #16] @ (80004a8 <(anonymous namespace)::DecrementPortClockRefCount(GPIO_TypeDef*)+0x30>)
  686. 8000496: 4805 ldr r0, [pc, #20] @ (80004ac <(anonymous namespace)::DecrementPortClockRefCount(GPIO_TypeDef*)+0x34>)
  687. 8000498: 217e movs r1, #126 @ 0x7e
  688. 800049a: f7ff fed7 bl 800024c <__assert_func>
  689. 800049e: 46c0 nop @ (mov r8, r8)
  690. 80004a0: 20000050 .word 0x20000050
  691. 80004a4: 08000d04 .word 0x08000d04
  692. 80004a8: 08000d38 .word 0x08000d38
  693. 80004ac: 08000cd4 .word 0x08000cd4
  694.  
  695. 080004b0 <mcu::stm32g070::Gpio::Gpio(std::span<mcu::stm32g070::Gpio::GpioConfig const, 4294967295u>)>:
  696.  
  697. } // namespace
  698.  
  699. namespace mcu::stm32g070 {
  700.  
  701. Gpio::Gpio(std::span<const GpioConfig> default_pin_configurations)
  702. 80004b0: b510 push {r4, lr}
  703. 80004b2: b082 sub sp, #8
  704. 80004b4: 466b mov r3, sp
  705. 80004b6: 9100 str r1, [sp, #0]
  706. 80004b8: 605a str r2, [r3, #4]
  707. : default_pin_cfg_{default_pin_configurations} {
  708. 80004ba: 0002 movs r2, r0
  709. 80004bc: cb12 ldmia r3!, {r1, r4}
  710. 80004be: c212 stmia r2!, {r1, r4}
  711. }
  712. 80004c0: b002 add sp, #8
  713. 80004c2: bd10 pop {r4, pc}
  714.  
  715. 080004c4 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)>:
  716. break;
  717. }
  718. }
  719. }
  720.  
  721. void Gpio::Configure(GpioId pin, const GpioConfig &config) {
  722. 80004c4: b5f8 push {r3, r4, r5, r6, r7, lr}
  723. 80004c6: 0005 movs r5, r0
  724. 80004c8: 000e movs r6, r1
  725. GPIO_TypeDef *port = GetPortRegister(pin);
  726. 80004ca: f7ff ff17 bl 80002fc <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)>
  727. 80004ce: 1e04 subs r4, r0, #0
  728. assert(port != nullptr);
  729. 80004d0: d00a beq.n 80004e8 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x24>
  730. uint8_t port_pin = pin & kPinMask;
  731. 80004d2: 200f movs r0, #15
  732. 80004d4: 4005 ands r5, r0
  733.  
  734. uint8_t mode_bit_value =
  735. (config.mode == mcu::stm32g070::Gpio::kInput) ? 0b00
  736. 80004d6: 7873 ldrb r3, [r6, #1]
  737. 80004d8: 2b02 cmp r3, #2
  738. 80004da: d00b beq.n 80004f4 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x30>
  739. 80004dc: 2b03 cmp r3, #3
  740. 80004de: d00b beq.n 80004f8 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x34>
  741. 80004e0: 2b01 cmp r3, #1
  742. 80004e2: d123 bne.n 800052c <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x68>
  743. 80004e4: 2700 movs r7, #0
  744. 80004e6: e008 b.n 80004fa <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x36>
  745. assert(port != nullptr);
  746. 80004e8: 4b25 ldr r3, [pc, #148] @ (8000580 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0xbc>)
  747. 80004ea: 4a26 ldr r2, [pc, #152] @ (8000584 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0xc0>)
  748. 80004ec: 4826 ldr r0, [pc, #152] @ (8000588 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0xc4>)
  749. 80004ee: 21c9 movs r1, #201 @ 0xc9
  750. 80004f0: f7ff feac bl 800024c <__assert_func>
  751. (config.mode == mcu::stm32g070::Gpio::kInput) ? 0b00
  752. 80004f4: 2701 movs r7, #1
  753. 80004f6: e000 b.n 80004fa <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x36>
  754. 80004f8: 2702 movs r7, #2
  755.  
  756. // TODO: Need to implement reference counting policy to disable the port
  757. // clock, but for now, just enable the port. Note that explicit setting to
  758. // analog mode assumes that the pin is being disabled. Analog usage is a
  759. // separate reference counting call that needs to be done in the ADC driver.
  760. if (config.mode == mcu::stm32g070::Gpio::kAnalog) {
  761. 80004fa: 2b00 cmp r3, #0
  762. 80004fc: d118 bne.n 8000530 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x6c>
  763. DecrementPortClockRefCount(port);
  764. 80004fe: 0020 movs r0, r4
  765. 8000500: f7ff ffba bl 8000478 <(anonymous namespace)::DecrementPortClockRefCount(GPIO_TypeDef*)>
  766. } else {
  767. IncrementPortClockRefCount(port);
  768. }
  769.  
  770. if (config.mode == mcu::stm32g070::Gpio::kInput) {
  771. 8000504: 7873 ldrb r3, [r6, #1]
  772. 8000506: 2b01 cmp r3, #1
  773. 8000508: d016 beq.n 8000538 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x74>
  774. SetPullResistor(port, port_pin, config.input_cfg.pull_resistor);
  775. } else if (config.mode == mcu::stm32g070::Gpio::kOutput) {
  776. 800050a: 2b02 cmp r3, #2
  777. 800050c: d01a beq.n 8000544 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x80>
  778. SetPullResistor(port, port_pin, config.output_cfg.pull_resistor);
  779. SetOutputConfig(port, port_pin, config.output_cfg.output_type,
  780. config.output_cfg.speed);
  781. } else if (config.mode == mcu::stm32g070::Gpio::kAnalog) {
  782. 800050e: 2b00 cmp r3, #0
  783. 8000510: d001 beq.n 8000516 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x52>
  784. // No-op since pull up/down is automatically disconnected in analog mode
  785. } else if (config.mode == mcu::stm32g070::Gpio::kAlternateFunc) {
  786. 8000512: 2b03 cmp r3, #3
  787. 8000514: d022 beq.n 800055c <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x98>
  788. config.af_cfg.speed);
  789. SetAltConfig(port, port_pin, config.af_cfg.alt_func);
  790. }
  791.  
  792. // Set GPIO mode last to avoid glitching
  793. port->MODER &= ~(0b11 << (port_pin << 1));
  794. 8000516: 6823 ldr r3, [r4, #0]
  795. 8000518: 006d lsls r5, r5, #1
  796. 800051a: 2203 movs r2, #3
  797. 800051c: 40aa lsls r2, r5
  798. 800051e: 4393 bics r3, r2
  799. 8000520: 6023 str r3, [r4, #0]
  800. port->MODER |= (mode_bit_value << (port_pin << 1));
  801. 8000522: 6823 ldr r3, [r4, #0]
  802. 8000524: 40af lsls r7, r5
  803. 8000526: 433b orrs r3, r7
  804. 8000528: 6023 str r3, [r4, #0]
  805. }
  806. 800052a: bdf8 pop {r3, r4, r5, r6, r7, pc}
  807. (config.mode == mcu::stm32g070::Gpio::kInput) ? 0b00
  808. 800052c: 2703 movs r7, #3
  809. 800052e: e7e4 b.n 80004fa <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x36>
  810. IncrementPortClockRefCount(port);
  811. 8000530: 0020 movs r0, r4
  812. 8000532: f7ff ff8d bl 8000450 <(anonymous namespace)::IncrementPortClockRefCount(GPIO_TypeDef*)>
  813. 8000536: e7e5 b.n 8000504 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x40>
  814. SetPullResistor(port, port_pin, config.input_cfg.pull_resistor);
  815. 8000538: 78b2 ldrb r2, [r6, #2]
  816. 800053a: 0029 movs r1, r5
  817. 800053c: 0020 movs r0, r4
  818. 800053e: f7ff fefb bl 8000338 <(anonymous namespace)::SetPullResistor(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioPullResistor)>
  819. 8000542: e7e8 b.n 8000516 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x52>
  820. SetPullResistor(port, port_pin, config.output_cfg.pull_resistor);
  821. 8000544: 7932 ldrb r2, [r6, #4]
  822. 8000546: 0029 movs r1, r5
  823. 8000548: 0020 movs r0, r4
  824. 800054a: f7ff fef5 bl 8000338 <(anonymous namespace)::SetPullResistor(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioPullResistor)>
  825. SetOutputConfig(port, port_pin, config.output_cfg.output_type,
  826. 800054e: 78b2 ldrb r2, [r6, #2]
  827. config.output_cfg.speed);
  828. 8000550: 78f3 ldrb r3, [r6, #3]
  829. SetOutputConfig(port, port_pin, config.output_cfg.output_type,
  830. 8000552: 0029 movs r1, r5
  831. 8000554: 0020 movs r0, r4
  832. 8000556: f7ff ff0a bl 800036e <(anonymous namespace)::SetOutputConfig(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioOutputType, mcu::stm32g070::Gpio::GpioOutputSpeed)>
  833. 800055a: e7dc b.n 8000516 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x52>
  834. SetPullResistor(port, port_pin, config.af_cfg.pull_resistor);
  835. 800055c: 7972 ldrb r2, [r6, #5]
  836. 800055e: 0029 movs r1, r5
  837. 8000560: 0020 movs r0, r4
  838. 8000562: f7ff fee9 bl 8000338 <(anonymous namespace)::SetPullResistor(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioPullResistor)>
  839. SetOutputConfig(port, port_pin, config.af_cfg.output_type,
  840. 8000566: 78f2 ldrb r2, [r6, #3]
  841. config.af_cfg.speed);
  842. 8000568: 7933 ldrb r3, [r6, #4]
  843. SetOutputConfig(port, port_pin, config.af_cfg.output_type,
  844. 800056a: 0029 movs r1, r5
  845. 800056c: 0020 movs r0, r4
  846. 800056e: f7ff fefe bl 800036e <(anonymous namespace)::SetOutputConfig(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioOutputType, mcu::stm32g070::Gpio::GpioOutputSpeed)>
  847. SetAltConfig(port, port_pin, config.af_cfg.alt_func);
  848. 8000572: 78b2 ldrb r2, [r6, #2]
  849. 8000574: 0029 movs r1, r5
  850. 8000576: 0020 movs r0, r4
  851. 8000578: f7ff ff12 bl 80003a0 <(anonymous namespace)::SetAltConfig(GPIO_TypeDef*, unsigned char, mcu::stm32g070::Gpio::GpioAltFunc)>
  852. 800057c: e7cb b.n 8000516 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)+0x52>
  853. 800057e: 46c0 nop @ (mov r8, r8)
  854. 8000580: 08000d74 .word 0x08000d74
  855. 8000584: 08000d84 .word 0x08000d84
  856. 8000588: 08000cd4 .word 0x08000cd4
  857.  
  858. 0800058c <mcu::stm32g070::Gpio::ConfigureAllToDefault()>:
  859. void Gpio::ConfigureAllToDefault() {
  860. 800058c: b570 push {r4, r5, r6, lr}
  861. _GLIBCXX_CONSTEXPR __normal_iterator() _GLIBCXX_NOEXCEPT
  862. : _M_current(_Iterator()) { }
  863.  
  864. explicit _GLIBCXX20_CONSTEXPR
  865. __normal_iterator(const _Iterator& __i) _GLIBCXX_NOEXCEPT
  866. : _M_current(__i) { }
  867. 800058e: 6805 ldr r5, [r0, #0]
  868. for (auto &config : default_pin_cfg_) {
  869. 8000590: 002c movs r4, r5
  870. { return this->_M_extent_value; }
  871. 8000592: 6842 ldr r2, [r0, #4]
  872. { return iterator(this->_M_ptr); }
  873.  
  874. [[nodiscard]]
  875. constexpr iterator
  876. end() const noexcept
  877. { return iterator(this->_M_ptr + this->size()); }
  878. 8000594: 0053 lsls r3, r2, #1
  879. 8000596: 189b adds r3, r3, r2
  880. 8000598: 005b lsls r3, r3, #1
  881. 800059a: 18ed adds r5, r5, r3
  882. 800059c: e004 b.n 80005a8 <mcu::stm32g070::Gpio::ConfigureAllToDefault()+0x1c>
  883. Gpio::Configure(config.pin, config);
  884. 800059e: 7820 ldrb r0, [r4, #0]
  885. 80005a0: 0021 movs r1, r4
  886. 80005a2: f7ff ff8f bl 80004c4 <mcu::stm32g070::Gpio::Configure(mcu::stm32g070::Gpio::GpioId, mcu::stm32g070::Gpio::GpioConfig const&)>
  887.  
  888. _GLIBCXX20_CONSTEXPR
  889. __normal_iterator&
  890. operator++() _GLIBCXX_NOEXCEPT
  891. {
  892. ++_M_current;
  893. 80005a6: 3406 adds r4, #6
  894. for (auto &config : default_pin_cfg_) {
  895. 80005a8: 42a5 cmp r5, r4
  896. 80005aa: d1f8 bne.n 800059e <mcu::stm32g070::Gpio::ConfigureAllToDefault()+0x12>
  897. }
  898. 80005ac: bd70 pop {r4, r5, r6, pc}
  899.  
  900. 080005ae <mcu::stm32g070::Gpio::Write(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::LogicLevel)>:
  901. uint8_t port_pin = pin & kPinMask;
  902. uint32_t value = port->IDR & (0b1 << port_pin);
  903. return value ? Gpio::LogicLevel::kHigh : Gpio::LogicLevel::kLow;
  904. }
  905.  
  906. void Gpio::Write(GpioId pin, Gpio::LogicLevel value) {
  907. 80005ae: b570 push {r4, r5, r6, lr}
  908. 80005b0: 0004 movs r4, r0
  909. 80005b2: 000d movs r5, r1
  910. GPIO_TypeDef *port = GetPortRegister(pin);
  911. 80005b4: f7ff fea2 bl 80002fc <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)>
  912. uint8_t port_pin = pin & kPinMask;
  913. 80005b8: 220f movs r2, #15
  914. 80005ba: 4022 ands r2, r4
  915. uint32_t mask = 0b1 << port_pin;
  916. 80005bc: 2301 movs r3, #1
  917. 80005be: 4093 lsls r3, r2
  918. if (value == Gpio::LogicLevel::kLow) {
  919. 80005c0: 2d01 cmp r5, #1
  920. 80005c2: d003 beq.n 80005cc <mcu::stm32g070::Gpio::Write(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::LogicLevel)+0x1e>
  921. port->ODR &= ~mask;
  922. } else {
  923. port->ODR |= mask;
  924. 80005c4: 6942 ldr r2, [r0, #20]
  925. 80005c6: 4313 orrs r3, r2
  926. 80005c8: 6143 str r3, [r0, #20]
  927. }
  928. }
  929. 80005ca: bd70 pop {r4, r5, r6, pc}
  930. port->ODR &= ~mask;
  931. 80005cc: 6942 ldr r2, [r0, #20]
  932. 80005ce: 439a bics r2, r3
  933. 80005d0: 6142 str r2, [r0, #20]
  934. 80005d2: e7fa b.n 80005ca <mcu::stm32g070::Gpio::Write(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::LogicLevel)+0x1c>
  935.  
  936. 080005d4 <mcu::stm32g070::Gpio::Toggle(mcu::stm32g070::Gpio::GpioId)>:
  937.  
  938. Gpio::LogicLevel Gpio::Toggle(GpioId pin) {
  939. 80005d4: b510 push {r4, lr}
  940. 80005d6: 0004 movs r4, r0
  941. GPIO_TypeDef *port = GetPortRegister(pin);
  942. 80005d8: f7ff fe90 bl 80002fc <(anonymous namespace)::GetPortRegister(mcu::stm32g070::Gpio::GpioId)>
  943. uint8_t port_pin = pin & kPinMask;
  944. 80005dc: 220f movs r2, #15
  945. 80005de: 4022 ands r2, r4
  946. uint32_t mask = 0b1 << port_pin;
  947. 80005e0: 2301 movs r3, #1
  948. 80005e2: 4093 lsls r3, r2
  949. uint32_t current_output_value = port->ODR & mask;
  950. 80005e4: 6942 ldr r2, [r0, #20]
  951. if (current_output_value) {
  952. 80005e6: 4213 tst r3, r2
  953. 80005e8: d004 beq.n 80005f4 <mcu::stm32g070::Gpio::Toggle(mcu::stm32g070::Gpio::GpioId)+0x20>
  954. port->ODR &= ~mask;
  955. 80005ea: 6942 ldr r2, [r0, #20]
  956. 80005ec: 439a bics r2, r3
  957. 80005ee: 6142 str r2, [r0, #20]
  958. return Gpio::LogicLevel::kLow;
  959. 80005f0: 2001 movs r0, #1
  960. } else {
  961. port->ODR |= mask;
  962. return Gpio::LogicLevel::kHigh;
  963. }
  964. }
  965. 80005f2: bd10 pop {r4, pc}
  966. port->ODR |= mask;
  967. 80005f4: 6942 ldr r2, [r0, #20]
  968. 80005f6: 4313 orrs r3, r2
  969. 80005f8: 6143 str r3, [r0, #20]
  970. return Gpio::LogicLevel::kHigh;
  971. 80005fa: 2000 movs r0, #0
  972. 80005fc: e7f9 b.n 80005f2 <mcu::stm32g070::Gpio::Toggle(mcu::stm32g070::Gpio::GpioId)+0x1e>
  973. ...
  974.  
  975. 08000600 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)>:
  976.  
  977. void Gpio::ConfigureInterrupt(GpioId pin, InterruptEvent interrupt_mode,
  978. InterruptDelegate callback) {
  979. 8000600: b5f0 push {r4, r5, r6, r7, lr}
  980. 8000602: 46c6 mov lr, r8
  981. 8000604: b500 push {lr}
  982. 8000606: 0006 movs r6, r0
  983. 8000608: 000d movs r5, r1
  984. uint8_t port_pin = pin & kPinMask;
  985. 800060a: 240f movs r4, #15
  986. 800060c: 4004 ands r4, r0
  987. return stub_ptr != nullptr;
  988. 800060e: 4b2f ldr r3, [pc, #188] @ (80006cc <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xcc>)
  989. 8000610: 0061 lsls r1, r4, #1
  990. 8000612: 1909 adds r1, r1, r4
  991. 8000614: 0089 lsls r1, r1, #2
  992. 8000616: 185b adds r3, r3, r1
  993. 8000618: 689b ldr r3, [r3, #8]
  994. auto &gpio_irq_info = irq_callback_table[port_pin];
  995. assert(!gpio_irq_info.callback.IsValid());
  996. 800061a: 2b00 cmp r3, #0
  997. 800061c: d13c bne.n 8000698 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0x98>
  998. gpio_irq_info.pin = pin;
  999. 800061e: 4b2b ldr r3, [pc, #172] @ (80006cc <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xcc>)
  1000. 8000620: 0061 lsls r1, r4, #1
  1001. 8000622: 1908 adds r0, r1, r4
  1002. 8000624: 0080 lsls r0, r0, #2
  1003. 8000626: 54c6 strb r6, [r0, r3]
  1004. object_ptr = other.object_ptr;
  1005. 8000628: 6817 ldr r7, [r2, #0]
  1006. 800062a: 1908 adds r0, r1, r4
  1007. 800062c: 0080 lsls r0, r0, #2
  1008. 800062e: 1818 adds r0, r3, r0
  1009. 8000630: 6047 str r7, [r0, #4]
  1010. stub_ptr = other.stub_ptr;
  1011. 8000632: 6852 ldr r2, [r2, #4]
  1012. 8000634: 6082 str r2, [r0, #8]
  1013. gpio_irq_info.callback = callback;
  1014. RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN;
  1015. 8000636: 4a26 ldr r2, [pc, #152] @ (80006d0 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xd0>)
  1016. 8000638: 6c13 ldr r3, [r2, #64] @ 0x40
  1017. 800063a: 2101 movs r1, #1
  1018. 800063c: 430b orrs r3, r1
  1019. 800063e: 6413 str r3, [r2, #64] @ 0x40
  1020.  
  1021. auto port_id = GetPortIdFromPin(pin);
  1022. 8000640: 0030 movs r0, r6
  1023. 8000642: f7ff ff13 bl 800046c <(anonymous namespace)::GetPortIdFromPin(mcu::stm32g070::Gpio::GpioId)>
  1024. 8000646: 4680 mov r8, r0
  1025. auto quadrant = port_pin >> 2;
  1026. 8000648: 08a3 lsrs r3, r4, #2
  1027. auto quadrant_line = port_pin & 0x3;
  1028. 800064a: 2203 movs r2, #3
  1029. 800064c: 4032 ands r2, r6
  1030. EXTI->EXTICR[quadrant] &= ~(0x2f << (quadrant_line << 3));
  1031. 800064e: 4921 ldr r1, [pc, #132] @ (80006d4 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xd4>)
  1032. 8000650: 3318 adds r3, #24
  1033. 8000652: 009b lsls r3, r3, #2
  1034. 8000654: 585f ldr r7, [r3, r1]
  1035. 8000656: 00d2 lsls r2, r2, #3
  1036. 8000658: 202f movs r0, #47 @ 0x2f
  1037. 800065a: 4090 lsls r0, r2
  1038. 800065c: 4387 bics r7, r0
  1039. 800065e: 505f str r7, [r3, r1]
  1040. EXTI->EXTICR[quadrant] |= (port_id << (quadrant_line << 3));
  1041. 8000660: 585f ldr r7, [r3, r1]
  1042. 8000662: 4640 mov r0, r8
  1043. 8000664: 4090 lsls r0, r2
  1044. 8000666: 4307 orrs r7, r0
  1045. 8000668: 505f str r7, [r3, r1]
  1046.  
  1047. if (interrupt_mode == InterruptEvent::kRisingEdge ||
  1048. 800066a: 2d00 cmp r5, #0
  1049. 800066c: d001 beq.n 8000672 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0x72>
  1050. 800066e: 2d02 cmp r5, #2
  1051. 8000670: d105 bne.n 800067e <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0x7e>
  1052. interrupt_mode == InterruptEvent::kBothEdges) {
  1053. EXTI->RTSR1 |= (1 << port_pin);
  1054. 8000672: 4918 ldr r1, [pc, #96] @ (80006d4 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xd4>)
  1055. 8000674: 680b ldr r3, [r1, #0]
  1056. 8000676: 2201 movs r2, #1
  1057. 8000678: 40a2 lsls r2, r4
  1058. 800067a: 4313 orrs r3, r2
  1059. 800067c: 600b str r3, [r1, #0]
  1060. }
  1061.  
  1062. if (interrupt_mode == InterruptEvent::kFallingEdge ||
  1063. 800067e: 3d01 subs r5, #1
  1064. 8000680: b2ed uxtb r5, r5
  1065. 8000682: 2d01 cmp r5, #1
  1066. 8000684: d90f bls.n 80006a6 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xa6>
  1067. interrupt_mode == InterruptEvent::kBothEdges) {
  1068. EXTI->FTSR1 |= (1 << port_pin);
  1069. }
  1070.  
  1071. if (port_pin < 2) {
  1072. 8000686: 230e movs r3, #14
  1073. 8000688: 4233 tst r3, r6
  1074. 800068a: d113 bne.n 80006b4 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xb4>
  1075. __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
  1076. {
  1077. if ((int32_t)(IRQn) >= 0)
  1078. {
  1079. __COMPILER_BARRIER();
  1080. NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  1081. 800068c: 4b12 ldr r3, [pc, #72] @ (80006d8 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xd8>)
  1082. 800068e: 2220 movs r2, #32
  1083. 8000690: 601a str r2, [r3, #0]
  1084. } else if (port_pin < 4) {
  1085. NVIC_EnableIRQ(EXTI2_3_IRQn);
  1086. } else {
  1087. NVIC_EnableIRQ(EXTI4_15_IRQn);
  1088. }
  1089. }
  1090. 8000692: bc80 pop {r7}
  1091. 8000694: 46b8 mov r8, r7
  1092. 8000696: bdf0 pop {r4, r5, r6, r7, pc}
  1093. assert(!gpio_irq_info.callback.IsValid());
  1094. 8000698: 4b10 ldr r3, [pc, #64] @ (80006dc <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xdc>)
  1095. 800069a: 4a11 ldr r2, [pc, #68] @ (80006e0 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xe0>)
  1096. 800069c: 218a movs r1, #138 @ 0x8a
  1097. 800069e: 4811 ldr r0, [pc, #68] @ (80006e4 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xe4>)
  1098. 80006a0: 0049 lsls r1, r1, #1
  1099. 80006a2: f7ff fdd3 bl 800024c <__assert_func>
  1100. EXTI->FTSR1 |= (1 << port_pin);
  1101. 80006a6: 490b ldr r1, [pc, #44] @ (80006d4 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xd4>)
  1102. 80006a8: 684b ldr r3, [r1, #4]
  1103. 80006aa: 2201 movs r2, #1
  1104. 80006ac: 40a2 lsls r2, r4
  1105. 80006ae: 4313 orrs r3, r2
  1106. 80006b0: 604b str r3, [r1, #4]
  1107. 80006b2: e7e8 b.n 8000686 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0x86>
  1108. } else if (port_pin < 4) {
  1109. 80006b4: 230c movs r3, #12
  1110. 80006b6: 4233 tst r3, r6
  1111. 80006b8: d103 bne.n 80006c2 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xc2>
  1112. 80006ba: 4b07 ldr r3, [pc, #28] @ (80006d8 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xd8>)
  1113. 80006bc: 2240 movs r2, #64 @ 0x40
  1114. 80006be: 601a str r2, [r3, #0]
  1115. __COMPILER_BARRIER();
  1116. }
  1117. }
  1118. 80006c0: e7e7 b.n 8000692 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0x92>
  1119. NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  1120. 80006c2: 4b05 ldr r3, [pc, #20] @ (80006d8 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0xd8>)
  1121. 80006c4: 2280 movs r2, #128 @ 0x80
  1122. 80006c6: 601a str r2, [r3, #0]
  1123. }
  1124. 80006c8: e7e3 b.n 8000692 <mcu::stm32g070::Gpio::ConfigureInterrupt(mcu::stm32g070::Gpio::GpioId, mcu::hal::gpio::InterruptEvent, rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>)+0x92>
  1125. 80006ca: 46c0 nop @ (mov r8, r8)
  1126. 80006cc: 2000005c .word 0x2000005c
  1127. 80006d0: 40021000 .word 0x40021000
  1128. 80006d4: 40021800 .word 0x40021800
  1129. 80006d8: e000e100 .word 0xe000e100
  1130. 80006dc: 08000f34 .word 0x08000f34
  1131. 80006e0: 08000f58 .word 0x08000f58
  1132. 80006e4: 08000cd4 .word 0x08000cd4
  1133.  
  1134. 080006e8 <rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>::operator()(mcu::stm32g070::Gpio::GpioId) const>:
  1135. ReturnType operator()(Args... args) const {
  1136. 80006e8: b510 push {r4, lr}
  1137. assert(stub_ptr != nullptr);
  1138. 80006ea: 6843 ldr r3, [r0, #4]
  1139. 80006ec: 2b00 cmp r3, #0
  1140. 80006ee: d002 beq.n 80006f6 <rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>::operator()(mcu::stm32g070::Gpio::GpioId) const+0xe>
  1141. return (*stub_ptr)(object_ptr, std::forward<Args>(args)...);
  1142. 80006f0: 6800 ldr r0, [r0, #0]
  1143. 80006f2: 4798 blx r3
  1144. }
  1145. 80006f4: bd10 pop {r4, pc}
  1146. assert(stub_ptr != nullptr);
  1147. 80006f6: 4b03 ldr r3, [pc, #12] @ (8000704 <rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>::operator()(mcu::stm32g070::Gpio::GpioId) const+0x1c>)
  1148. 80006f8: 4a03 ldr r2, [pc, #12] @ (8000708 <rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>::operator()(mcu::stm32g070::Gpio::GpioId) const+0x20>)
  1149. 80006fa: 4804 ldr r0, [pc, #16] @ (800070c <rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>::operator()(mcu::stm32g070::Gpio::GpioId) const+0x24>)
  1150. 80006fc: 214a movs r1, #74 @ 0x4a
  1151. 80006fe: f7ff fda5 bl 800024c <__assert_func>
  1152. 8000702: 46c0 nop @ (mov r8, r8)
  1153. 8000704: 08000fb8 .word 0x08000fb8
  1154. 8000708: 08000fcc .word 0x08000fcc
  1155. 800070c: 0800105c .word 0x0800105c
  1156.  
  1157. 08000710 <(anonymous namespace)::CommonISRHandler(unsigned short)>:
  1158. void CommonISRHandler([[maybe_unused]] uint16_t exti_set_mask) {
  1159. 8000710: b570 push {r4, r5, r6, lr}
  1160. 8000712: 0005 movs r5, r0
  1161. while (exti_set_mask) {
  1162. 8000714: e00b b.n 800072e <(anonymous namespace)::CommonISRHandler(unsigned short)+0x1e>
  1163. EXTI->RPR1 &= (1 << index);
  1164. 8000716: 4a14 ldr r2, [pc, #80] @ (8000768 <(anonymous namespace)::CommonISRHandler(unsigned short)+0x58>)
  1165. 8000718: 68d1 ldr r1, [r2, #12]
  1166. 800071a: 2301 movs r3, #1
  1167. 800071c: 40a3 lsls r3, r4
  1168. 800071e: 4019 ands r1, r3
  1169. 8000720: 60d1 str r1, [r2, #12]
  1170. EXTI->FPR1 &= (1 << index);
  1171. 8000722: 6911 ldr r1, [r2, #16]
  1172. 8000724: 4019 ands r1, r3
  1173. 8000726: 6111 str r1, [r2, #16]
  1174. exti_set_mask &= ~(1 << index);
  1175. 8000728: 43db mvns r3, r3
  1176. 800072a: b21b sxth r3, r3
  1177. 800072c: 401d ands r5, r3
  1178. while (exti_set_mask) {
  1179. 800072e: 2d00 cmp r5, #0
  1180. 8000730: d018 beq.n 8000764 <(anonymous namespace)::CommonISRHandler(unsigned short)+0x54>
  1181. uint8_t index = __builtin_ctz(exti_set_mask) & 0xf;
  1182. 8000732: 0028 movs r0, r5
  1183. 8000734: f7ff fcc0 bl 80000b8 <__ctzsi2>
  1184. 8000738: 240f movs r4, #15
  1185. 800073a: 4004 ands r4, r0
  1186. return stub_ptr != nullptr;
  1187. 800073c: 4b0b ldr r3, [pc, #44] @ (800076c <(anonymous namespace)::CommonISRHandler(unsigned short)+0x5c>)
  1188. 800073e: 0062 lsls r2, r4, #1
  1189. 8000740: 1912 adds r2, r2, r4
  1190. 8000742: 0092 lsls r2, r2, #2
  1191. 8000744: 189b adds r3, r3, r2
  1192. 8000746: 689b ldr r3, [r3, #8]
  1193. if (gpio_irq_info.callback.IsValid()) {
  1194. 8000748: 2b00 cmp r3, #0
  1195. 800074a: d0e4 beq.n 8000716 <(anonymous namespace)::CommonISRHandler(unsigned short)+0x6>
  1196. gpio_irq_info.callback(gpio_irq_info.pin);
  1197. 800074c: 4a07 ldr r2, [pc, #28] @ (800076c <(anonymous namespace)::CommonISRHandler(unsigned short)+0x5c>)
  1198. 800074e: 0060 lsls r0, r4, #1
  1199. 8000750: 1901 adds r1, r0, r4
  1200. 8000752: 0089 lsls r1, r1, #2
  1201. 8000754: 5c89 ldrb r1, [r1, r2]
  1202. 8000756: 1900 adds r0, r0, r4
  1203. 8000758: 0080 lsls r0, r0, #2
  1204. 800075a: 1880 adds r0, r0, r2
  1205. 800075c: 3004 adds r0, #4
  1206. 800075e: f7ff ffc3 bl 80006e8 <rtlib::Delegate<void (mcu::stm32g070::Gpio::GpioId)>::operator()(mcu::stm32g070::Gpio::GpioId) const>
  1207. 8000762: e7d8 b.n 8000716 <(anonymous namespace)::CommonISRHandler(unsigned short)+0x6>
  1208. }
  1209. 8000764: bd70 pop {r4, r5, r6, pc}
  1210. 8000766: 46c0 nop @ (mov r8, r8)
  1211. 8000768: 40021800 .word 0x40021800
  1212. 800076c: 2000005c .word 0x2000005c
  1213.  
  1214. 08000770 <EXTI0_1_IRQHandler>:
  1215. extern "C" void EXTI0_1_IRQHandler(void) {
  1216. 8000770: b510 push {r4, lr}
  1217. uint16_t mask = SYSCFG->IT_LINE_SR[5] & 0b11;
  1218. 8000772: 4a04 ldr r2, [pc, #16] @ (8000784 <EXTI0_1_IRQHandler+0x14>)
  1219. 8000774: 2394 movs r3, #148 @ 0x94
  1220. 8000776: 58d0 ldr r0, [r2, r3]
  1221. 8000778: 3b91 subs r3, #145 @ 0x91
  1222. 800077a: 4018 ands r0, r3
  1223. CommonISRHandler(mask);
  1224. 800077c: f7ff ffc8 bl 8000710 <(anonymous namespace)::CommonISRHandler(unsigned short)>
  1225. }
  1226. 8000780: bd10 pop {r4, pc}
  1227. 8000782: 46c0 nop @ (mov r8, r8)
  1228. 8000784: 40010000 .word 0x40010000
  1229.  
  1230. 08000788 <EXTI2_3_IRQHandler>:
  1231. extern "C" void EXTI2_3_IRQHandler(void) {
  1232. 8000788: b510 push {r4, lr}
  1233. uint16_t mask = (SYSCFG->IT_LINE_SR[6] & 0b11) << 2;
  1234. 800078a: 4a04 ldr r2, [pc, #16] @ (800079c <EXTI2_3_IRQHandler+0x14>)
  1235. 800078c: 2398 movs r3, #152 @ 0x98
  1236. 800078e: 58d0 ldr r0, [r2, r3]
  1237. 8000790: 0080 lsls r0, r0, #2
  1238. 8000792: 3b8c subs r3, #140 @ 0x8c
  1239. 8000794: 4018 ands r0, r3
  1240. CommonISRHandler(mask);
  1241. 8000796: f7ff ffbb bl 8000710 <(anonymous namespace)::CommonISRHandler(unsigned short)>
  1242. }
  1243. 800079a: bd10 pop {r4, pc}
  1244. 800079c: 40010000 .word 0x40010000
  1245.  
  1246. 080007a0 <EXTI4_15_IRQHandler>:
  1247. extern "C" void EXTI4_15_IRQHandler(void) {
  1248. 80007a0: b510 push {r4, lr}
  1249. uint16_t mask = (SYSCFG->IT_LINE_SR[7] & 0xfff) << 4;
  1250. 80007a2: 4a04 ldr r2, [pc, #16] @ (80007b4 <EXTI4_15_IRQHandler+0x14>)
  1251. 80007a4: 239c movs r3, #156 @ 0x9c
  1252. 80007a6: 58d0 ldr r0, [r2, r3]
  1253. 80007a8: b280 uxth r0, r0
  1254. 80007aa: 0100 lsls r0, r0, #4
  1255. 80007ac: b280 uxth r0, r0
  1256. CommonISRHandler(mask);
  1257. 80007ae: f7ff ffaf bl 8000710 <(anonymous namespace)::CommonISRHandler(unsigned short)>
  1258. }
  1259. 80007b2: bd10 pop {r4, pc}
  1260. 80007b4: 40010000 .word 0x40010000
  1261.  
  1262. 080007b8 <mcu::stm32g070::SysClock::Set64MHzSysClk()>:
  1263. // APB prescaled by 4 for 16 MHz PCLK
  1264. static void Set64MHzSysClk(void) {
  1265. // NOTE: Assume POR conditions at this point: SYSCLK = HSI @ 16 MHz
  1266.  
  1267. // Disable PLL
  1268. RCC->CR &= (uint32_t)(~RCC_CR_PLLON);
  1269. 80007b8: 4a21 ldr r2, [pc, #132] @ (8000840 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x88>)
  1270. 80007ba: 6813 ldr r3, [r2, #0]
  1271. 80007bc: 4921 ldr r1, [pc, #132] @ (8000844 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x8c>)
  1272. 80007be: 400b ands r3, r1
  1273. 80007c0: 6013 str r3, [r2, #0]
  1274. while ((RCC->CR & RCC_CR_PLLRDY) != 0);
  1275. 80007c2: 4b1f ldr r3, [pc, #124] @ (8000840 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x88>)
  1276. 80007c4: 681b ldr r3, [r3, #0]
  1277. 80007c6: 019b lsls r3, r3, #6
  1278. 80007c8: d4fb bmi.n 80007c2 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0xa>
  1279.  
  1280. // Set flash latency to 2 wait states
  1281. FLASH->ACR &= (uint32_t)(~FLASH_ACR_LATENCY);
  1282. 80007ca: 4b1f ldr r3, [pc, #124] @ (8000848 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x90>)
  1283. 80007cc: 681a ldr r2, [r3, #0]
  1284. 80007ce: 2107 movs r1, #7
  1285. 80007d0: 438a bics r2, r1
  1286. 80007d2: 601a str r2, [r3, #0]
  1287. FLASH->ACR |= FLASH_ACR_LATENCY_1;
  1288. 80007d4: 681a ldr r2, [r3, #0]
  1289. 80007d6: 3905 subs r1, #5
  1290. 80007d8: 430a orrs r2, r1
  1291. 80007da: 601a str r2, [r3, #0]
  1292. while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_ACR_LATENCY_1);
  1293. 80007dc: 4b1a ldr r3, [pc, #104] @ (8000848 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x90>)
  1294. 80007de: 681a ldr r2, [r3, #0]
  1295. 80007e0: 2307 movs r3, #7
  1296. 80007e2: 4013 ands r3, r2
  1297. 80007e4: 2b02 cmp r3, #2
  1298. 80007e6: d1f9 bne.n 80007dc <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x24>
  1299.  
  1300. // Enable instruction prefech & cache
  1301. FLASH->ACR |= FLASH_ACR_PRFTEN;
  1302. 80007e8: 4b17 ldr r3, [pc, #92] @ (8000848 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x90>)
  1303. 80007ea: 6819 ldr r1, [r3, #0]
  1304. 80007ec: 2280 movs r2, #128 @ 0x80
  1305. 80007ee: 0052 lsls r2, r2, #1
  1306. 80007f0: 430a orrs r2, r1
  1307. 80007f2: 601a str r2, [r3, #0]
  1308. FLASH->ACR |= FLASH_ACR_ICEN;
  1309. 80007f4: 6819 ldr r1, [r3, #0]
  1310. 80007f6: 2280 movs r2, #128 @ 0x80
  1311. 80007f8: 0092 lsls r2, r2, #2
  1312. 80007fa: 430a orrs r2, r1
  1313. 80007fc: 601a str r2, [r3, #0]
  1314.  
  1315. // fVCO = HSI * (N/M) = 16 MHz * 16 = 256 MHz
  1316. // fPLLR = fVCO / 4 = 64 MHz
  1317. RCC->PLLCFGR = (0b011 << RCC_PLLCFGR_PLLR_Pos) | RCC_PLLCFGR_PLLREN |
  1318. 80007fe: 4b10 ldr r3, [pc, #64] @ (8000840 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x88>)
  1319. 8000800: 4a12 ldr r2, [pc, #72] @ (800084c <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x94>)
  1320. 8000802: 60da str r2, [r3, #12]
  1321. (0b100000 << RCC_PLLCFGR_PLLN_Pos) |
  1322. (0b001 << RCC_PLLCFGR_PLLM_Pos) | RCC_PLLCFGR_PLLSRC_1;
  1323.  
  1324. // Set APB prescalar to /4 for PCLK = 16 Mhz
  1325. RCC->CFGR &= ~(RCC_CFGR_PPRE);
  1326. 8000804: 689a ldr r2, [r3, #8]
  1327. 8000806: 4912 ldr r1, [pc, #72] @ (8000850 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x98>)
  1328. 8000808: 400a ands r2, r1
  1329. 800080a: 609a str r2, [r3, #8]
  1330. RCC->CFGR |= (0b101 << RCC_CFGR_PPRE_Pos);
  1331. 800080c: 6899 ldr r1, [r3, #8]
  1332. 800080e: 22a0 movs r2, #160 @ 0xa0
  1333. 8000810: 01d2 lsls r2, r2, #7
  1334. 8000812: 430a orrs r2, r1
  1335. 8000814: 609a str r2, [r3, #8]
  1336.  
  1337. // Enable PLL
  1338. RCC->CR |= RCC_CR_PLLON;
  1339. 8000816: 6819 ldr r1, [r3, #0]
  1340. 8000818: 2280 movs r2, #128 @ 0x80
  1341. 800081a: 0452 lsls r2, r2, #17
  1342. 800081c: 430a orrs r2, r1
  1343. 800081e: 601a str r2, [r3, #0]
  1344. while ((RCC->CR & RCC_CR_PLLRDY) == 0);
  1345. 8000820: 4b07 ldr r3, [pc, #28] @ (8000840 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x88>)
  1346. 8000822: 681b ldr r3, [r3, #0]
  1347. 8000824: 019b lsls r3, r3, #6
  1348. 8000826: d5fb bpl.n 8000820 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x68>
  1349.  
  1350. // Use PLLRCLK as clock source for SYSCLK
  1351. RCC->CFGR |= (uint32_t)(RCC_CFGR_SW_1);
  1352. 8000828: 4a05 ldr r2, [pc, #20] @ (8000840 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x88>)
  1353. 800082a: 6893 ldr r3, [r2, #8]
  1354. 800082c: 2102 movs r1, #2
  1355. 800082e: 430b orrs r3, r1
  1356. 8000830: 6093 str r3, [r2, #8]
  1357. while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1);
  1358. 8000832: 4b03 ldr r3, [pc, #12] @ (8000840 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x88>)
  1359. 8000834: 689a ldr r2, [r3, #8]
  1360. 8000836: 2338 movs r3, #56 @ 0x38
  1361. 8000838: 4013 ands r3, r2
  1362. 800083a: 2b10 cmp r3, #16
  1363. 800083c: d1f9 bne.n 8000832 <mcu::stm32g070::SysClock::Set64MHzSysClk()+0x7a>
  1364. }
  1365. 800083e: 4770 bx lr
  1366. 8000840: 40021000 .word 0x40021000
  1367. 8000844: feffffff .word 0xfeffffff
  1368. 8000848: 40022000 .word 0x40022000
  1369. 800084c: 70002012 .word 0x70002012
  1370. 8000850: ffff8fff .word 0xffff8fff
  1371.  
  1372. 08000854 <mcu::stm32g070::SysClock::Init()>:
  1373.  
  1374. void Init() {
  1375. 8000854: b510 push {r4, lr}
  1376. Set64MHzSysClk();
  1377. 8000856: f7ff ffaf bl 80007b8 <mcu::stm32g070::SysClock::Set64MHzSysClk()>
  1378. }
  1379. 800085a: bd10 pop {r4, pc}
  1380.  
  1381. 0800085c <(anonymous namespace)::GetUartController(mcu::stm32g070::Uart::UartId)>:
  1382.  
  1383. namespace {
  1384. USART_TypeDef *GetUartController(mcu::stm32g070::Uart::UartId id) {
  1385. static constexpr USART_TypeDef *table[mcu::stm32g070::Uart::kNumUartId] = {
  1386. USART1, USART2, USART3, USART4};
  1387. return table[id];
  1388. 800085c: 4b01 ldr r3, [pc, #4] @ (8000864 <(anonymous namespace)::GetUartController(mcu::stm32g070::Uart::UartId)+0x8>)
  1389. 800085e: 0080 lsls r0, r0, #2
  1390. 8000860: 58c0 ldr r0, [r0, r3]
  1391. }
  1392. 8000862: 4770 bx lr
  1393. 8000864: 0800113c .word 0x0800113c
  1394.  
  1395. 08000868 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)>:
  1396.  
  1397. void EnableUartClock(mcu::stm32g070::Uart::UartId id) {
  1398. if (id == mcu::stm32g070::Uart::kUart1) {
  1399. 8000868: 2800 cmp r0, #0
  1400. 800086a: d106 bne.n 800087a <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x12>
  1401. RCC->APBENR2 |= RCC_APBENR2_USART1EN;
  1402. 800086c: 4a10 ldr r2, [pc, #64] @ (80008b0 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x48>)
  1403. 800086e: 6c11 ldr r1, [r2, #64] @ 0x40
  1404. 8000870: 2380 movs r3, #128 @ 0x80
  1405. 8000872: 01db lsls r3, r3, #7
  1406. 8000874: 430b orrs r3, r1
  1407. 8000876: 6413 str r3, [r2, #64] @ 0x40
  1408. } else if (id == mcu::stm32g070::Uart::kUart3) {
  1409. RCC->APBENR1 |= RCC_APBENR1_USART3EN;
  1410. } else if (id == mcu::stm32g070::Uart::kUart4) {
  1411. RCC->APBENR1 |= RCC_APBENR1_USART4EN;
  1412. }
  1413. }
  1414. 8000878: 4770 bx lr
  1415. } else if (id == mcu::stm32g070::Uart::kUart2) {
  1416. 800087a: 2801 cmp r0, #1
  1417. 800087c: d00a beq.n 8000894 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x2c>
  1418. } else if (id == mcu::stm32g070::Uart::kUart3) {
  1419. 800087e: 2802 cmp r0, #2
  1420. 8000880: d00f beq.n 80008a2 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x3a>
  1421. } else if (id == mcu::stm32g070::Uart::kUart4) {
  1422. 8000882: 2803 cmp r0, #3
  1423. 8000884: d1f8 bne.n 8000878 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x10>
  1424. RCC->APBENR1 |= RCC_APBENR1_USART4EN;
  1425. 8000886: 4a0a ldr r2, [pc, #40] @ (80008b0 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x48>)
  1426. 8000888: 6bd1 ldr r1, [r2, #60] @ 0x3c
  1427. 800088a: 2380 movs r3, #128 @ 0x80
  1428. 800088c: 031b lsls r3, r3, #12
  1429. 800088e: 430b orrs r3, r1
  1430. 8000890: 63d3 str r3, [r2, #60] @ 0x3c
  1431. }
  1432. 8000892: e7f1 b.n 8000878 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x10>
  1433. RCC->APBENR1 |= RCC_APBENR1_USART2EN;
  1434. 8000894: 4a06 ldr r2, [pc, #24] @ (80008b0 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x48>)
  1435. 8000896: 6bd1 ldr r1, [r2, #60] @ 0x3c
  1436. 8000898: 2380 movs r3, #128 @ 0x80
  1437. 800089a: 029b lsls r3, r3, #10
  1438. 800089c: 430b orrs r3, r1
  1439. 800089e: 63d3 str r3, [r2, #60] @ 0x3c
  1440. 80008a0: e7ea b.n 8000878 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x10>
  1441. RCC->APBENR1 |= RCC_APBENR1_USART3EN;
  1442. 80008a2: 4a03 ldr r2, [pc, #12] @ (80008b0 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x48>)
  1443. 80008a4: 6bd1 ldr r1, [r2, #60] @ 0x3c
  1444. 80008a6: 2380 movs r3, #128 @ 0x80
  1445. 80008a8: 02db lsls r3, r3, #11
  1446. 80008aa: 430b orrs r3, r1
  1447. 80008ac: 63d3 str r3, [r2, #60] @ 0x3c
  1448. 80008ae: e7e3 b.n 8000878 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)+0x10>
  1449. 80008b0: 40021000 .word 0x40021000
  1450.  
  1451. 080008b4 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)>:
  1452.  
  1453. void DisableUartClock(mcu::stm32g070::Uart::UartId id) {
  1454. if (id == mcu::stm32g070::Uart::kUart1) {
  1455. 80008b4: 2800 cmp r0, #0
  1456. 80008b6: d105 bne.n 80008c4 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x10>
  1457. RCC->APBENR2 &= ~RCC_APBENR2_USART1EN;
  1458. 80008b8: 4a0e ldr r2, [pc, #56] @ (80008f4 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x40>)
  1459. 80008ba: 6c13 ldr r3, [r2, #64] @ 0x40
  1460. 80008bc: 490e ldr r1, [pc, #56] @ (80008f8 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x44>)
  1461. 80008be: 400b ands r3, r1
  1462. 80008c0: 6413 str r3, [r2, #64] @ 0x40
  1463. } else if (id == mcu::stm32g070::Uart::kUart3) {
  1464. RCC->APBENR1 &= ~RCC_APBENR1_USART3EN;
  1465. } else if (id == mcu::stm32g070::Uart::kUart4) {
  1466. RCC->APBENR1 &= ~RCC_APBENR1_USART4EN;
  1467. }
  1468. }
  1469. 80008c2: 4770 bx lr
  1470. } else if (id == mcu::stm32g070::Uart::kUart2) {
  1471. 80008c4: 2801 cmp r0, #1
  1472. 80008c6: d009 beq.n 80008dc <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x28>
  1473. } else if (id == mcu::stm32g070::Uart::kUart3) {
  1474. 80008c8: 2802 cmp r0, #2
  1475. 80008ca: d00d beq.n 80008e8 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x34>
  1476. } else if (id == mcu::stm32g070::Uart::kUart4) {
  1477. 80008cc: 2803 cmp r0, #3
  1478. 80008ce: d1f8 bne.n 80008c2 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0xe>
  1479. RCC->APBENR1 &= ~RCC_APBENR1_USART4EN;
  1480. 80008d0: 4a08 ldr r2, [pc, #32] @ (80008f4 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x40>)
  1481. 80008d2: 6bd3 ldr r3, [r2, #60] @ 0x3c
  1482. 80008d4: 4909 ldr r1, [pc, #36] @ (80008fc <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x48>)
  1483. 80008d6: 400b ands r3, r1
  1484. 80008d8: 63d3 str r3, [r2, #60] @ 0x3c
  1485. }
  1486. 80008da: e7f2 b.n 80008c2 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0xe>
  1487. RCC->APBENR1 &= ~RCC_APBENR1_USART2EN;
  1488. 80008dc: 4a05 ldr r2, [pc, #20] @ (80008f4 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x40>)
  1489. 80008de: 6bd3 ldr r3, [r2, #60] @ 0x3c
  1490. 80008e0: 4907 ldr r1, [pc, #28] @ (8000900 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x4c>)
  1491. 80008e2: 400b ands r3, r1
  1492. 80008e4: 63d3 str r3, [r2, #60] @ 0x3c
  1493. 80008e6: e7ec b.n 80008c2 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0xe>
  1494. RCC->APBENR1 &= ~RCC_APBENR1_USART3EN;
  1495. 80008e8: 4a02 ldr r2, [pc, #8] @ (80008f4 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x40>)
  1496. 80008ea: 6bd3 ldr r3, [r2, #60] @ 0x3c
  1497. 80008ec: 4905 ldr r1, [pc, #20] @ (8000904 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0x50>)
  1498. 80008ee: 400b ands r3, r1
  1499. 80008f0: 63d3 str r3, [r2, #60] @ 0x3c
  1500. 80008f2: e7e6 b.n 80008c2 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)+0xe>
  1501. 80008f4: 40021000 .word 0x40021000
  1502. 80008f8: ffffbfff .word 0xffffbfff
  1503. 80008fc: fff7ffff .word 0xfff7ffff
  1504. 8000900: fffdffff .word 0xfffdffff
  1505. 8000904: fffbffff .word 0xfffbffff
  1506.  
  1507. 08000908 <mcu::stm32g070::Uart::Uart(mcu::stm32g070::Uart::UartConfig const&)>:
  1508. } // namespace
  1509.  
  1510. namespace mcu::stm32g070 {
  1511. Uart::Uart(UartConfig const &config) : config_{config}, tx_busy_{false} {
  1512. 8000908: 6001 str r1, [r0, #0]
  1513. 800090a: 2300 movs r3, #0
  1514. 800090c: 7103 strb r3, [r0, #4]
  1515. Delegate() = default;
  1516. 800090e: 6083 str r3, [r0, #8]
  1517. 8000910: 60c3 str r3, [r0, #12]
  1518. 8000912: 6103 str r3, [r0, #16]
  1519. 8000914: 6143 str r3, [r0, #20]
  1520. }
  1521. 8000916: 4770 bx lr
  1522.  
  1523. 08000918 <mcu::stm32g070::Uart::Init()>:
  1524.  
  1525. void Uart::Init() {
  1526. 8000918: b570 push {r4, r5, r6, lr}
  1527. 800091a: 0004 movs r4, r0
  1528. auto *uart_ctrl = GetUartController(config_.uart_id);
  1529. 800091c: 6803 ldr r3, [r0, #0]
  1530. 800091e: 781e ldrb r6, [r3, #0]
  1531. 8000920: 0030 movs r0, r6
  1532. 8000922: f7ff ff9b bl 800085c <(anonymous namespace)::GetUartController(mcu::stm32g070::Uart::UartId)>
  1533. 8000926: 0005 movs r5, r0
  1534. EnableUartClock(config_.uart_id);
  1535. 8000928: 0030 movs r0, r6
  1536. 800092a: f7ff ff9d bl 8000868 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)>
  1537. uart_ctrl->CR1 &= ~USART_CR1_UE;
  1538. 800092e: 682b ldr r3, [r5, #0]
  1539. 8000930: 2201 movs r2, #1
  1540. 8000932: 4393 bics r3, r2
  1541. 8000934: 602b str r3, [r5, #0]
  1542. assert(config_.baud_rate == mcu::hal::uart::k115200);
  1543. 8000936: 6823 ldr r3, [r4, #0]
  1544. 8000938: 685a ldr r2, [r3, #4]
  1545. 800093a: 23e1 movs r3, #225 @ 0xe1
  1546. 800093c: 025b lsls r3, r3, #9
  1547. 800093e: 429a cmp r2, r3
  1548. 8000940: d106 bne.n 8000950 <mcu::stm32g070::Uart::Init()+0x38>
  1549. uart_ctrl->BRR = 138; // For PCLK = 16 MHz
  1550. 8000942: 238a movs r3, #138 @ 0x8a
  1551. 8000944: 60eb str r3, [r5, #12]
  1552. DisableUartClock(config_.uart_id);
  1553. 8000946: 6823 ldr r3, [r4, #0]
  1554. 8000948: 7818 ldrb r0, [r3, #0]
  1555. 800094a: f7ff ffb3 bl 80008b4 <(anonymous namespace)::DisableUartClock(mcu::stm32g070::Uart::UartId)>
  1556. }
  1557. 800094e: bd70 pop {r4, r5, r6, pc}
  1558. assert(config_.baud_rate == mcu::hal::uart::k115200);
  1559. 8000950: 4b02 ldr r3, [pc, #8] @ (800095c <mcu::stm32g070::Uart::Init()+0x44>)
  1560. 8000952: 4a03 ldr r2, [pc, #12] @ (8000960 <mcu::stm32g070::Uart::Init()+0x48>)
  1561. 8000954: 4803 ldr r0, [pc, #12] @ (8000964 <mcu::stm32g070::Uart::Init()+0x4c>)
  1562. 8000956: 212d movs r1, #45 @ 0x2d
  1563. 8000958: f7ff fc78 bl 800024c <__assert_func>
  1564. 800095c: 08001084 .word 0x08001084
  1565. 8000960: 080010b4 .word 0x080010b4
  1566. 8000964: 080010d8 .word 0x080010d8
  1567.  
  1568. 08000968 <mcu::stm32g070::Uart::Enable()>:
  1569.  
  1570. void Uart::Enable() {
  1571. 8000968: b510 push {r4, lr}
  1572. 800096a: 0004 movs r4, r0
  1573. EnableUartClock(config_.uart_id);
  1574. 800096c: 6803 ldr r3, [r0, #0]
  1575. 800096e: 7818 ldrb r0, [r3, #0]
  1576. 8000970: f7ff ff7a bl 8000868 <(anonymous namespace)::EnableUartClock(mcu::stm32g070::Uart::UartId)>
  1577. auto *uart_ctrl = GetUartController(config_.uart_id);
  1578. 8000974: 6823 ldr r3, [r4, #0]
  1579. 8000976: 7818 ldrb r0, [r3, #0]
  1580. 8000978: f7ff ff70 bl 800085c <(anonymous namespace)::GetUartController(mcu::stm32g070::Uart::UartId)>
  1581. uart_ctrl->CR1 |= USART_CR1_UE | USART_CR1_TE;
  1582. 800097c: 6803 ldr r3, [r0, #0]
  1583. 800097e: 2209 movs r2, #9
  1584. 8000980: 4313 orrs r3, r2
  1585. 8000982: 6003 str r3, [r0, #0]
  1586. }
  1587. 8000984: bd10 pop {r4, pc}
  1588.  
  1589. 08000986 <mcu::stm32g070::Uart::Transmit(unsigned char const*, unsigned int)>:
  1590. auto *uart_ctrl = GetUartController(config_.uart_id);
  1591. uart_ctrl->CR1 &= ~(USART_CR1_UE | USART_CR1_TE);
  1592. DisableUartClock(config_.uart_id);
  1593. }
  1594.  
  1595. void Uart::Transmit(const uint8_t *data, size_t len) {
  1596. 8000986: b570 push {r4, r5, r6, lr}
  1597. 8000988: 000d movs r5, r1
  1598. 800098a: 0014 movs r4, r2
  1599. auto *uart_ctrl = GetUartController(config_.uart_id);
  1600. 800098c: 6803 ldr r3, [r0, #0]
  1601. 800098e: 7818 ldrb r0, [r3, #0]
  1602. 8000990: f7ff ff64 bl 800085c <(anonymous namespace)::GetUartController(mcu::stm32g070::Uart::UartId)>
  1603. while (len--) {
  1604. 8000994: e006 b.n 80009a4 <mcu::stm32g070::Uart::Transmit(unsigned char const*, unsigned int)+0x1e>
  1605. while ((uart_ctrl->ISR & USART_ISR_TXE_TXFNF) == 0);
  1606. 8000996: 69c3 ldr r3, [r0, #28]
  1607. 8000998: 061b lsls r3, r3, #24
  1608. 800099a: d5fc bpl.n 8000996 <mcu::stm32g070::Uart::Transmit(unsigned char const*, unsigned int)+0x10>
  1609. uart_ctrl->TDR = *data++;
  1610. 800099c: 782b ldrb r3, [r5, #0]
  1611. 800099e: 6283 str r3, [r0, #40] @ 0x28
  1612. while (len--) {
  1613. 80009a0: 0014 movs r4, r2
  1614. uart_ctrl->TDR = *data++;
  1615. 80009a2: 3501 adds r5, #1
  1616. while (len--) {
  1617. 80009a4: 1e62 subs r2, r4, #1
  1618. 80009a6: 2c00 cmp r4, #0
  1619. 80009a8: d1f5 bne.n 8000996 <mcu::stm32g070::Uart::Transmit(unsigned char const*, unsigned int)+0x10>
  1620. }
  1621. }
  1622. 80009aa: bd70 pop {r4, r5, r6, pc}
  1623.  
  1624. 080009ac <Reset_Handler>:
  1625.  
  1626. .section .text.Reset_Handler
  1627. .weak Reset_Handler
  1628. .type Reset_Handler, %function
  1629. Reset_Handler:
  1630. ldr r0, =_estack
  1631. 80009ac: 480d ldr r0, [pc, #52] @ (80009e4 <LoopForever+0x2>)
  1632. mov sp, r0 /* set stack pointer */
  1633. 80009ae: 4685 mov sp, r0
  1634.  
  1635. /* Call the clock system initialization function.*/
  1636. bl SystemInit
  1637. 80009b0: f000 f825 bl 80009fe <SystemInit>
  1638.  
  1639. /* Copy the data segment initializers from flash to SRAM */
  1640. ldr r0, =_sdata
  1641. 80009b4: 480c ldr r0, [pc, #48] @ (80009e8 <LoopForever+0x6>)
  1642. ldr r1, =_edata
  1643. 80009b6: 490d ldr r1, [pc, #52] @ (80009ec <LoopForever+0xa>)
  1644. ldr r2, =_sidata
  1645. 80009b8: 4a0d ldr r2, [pc, #52] @ (80009f0 <LoopForever+0xe>)
  1646. movs r3, #0
  1647. 80009ba: 2300 movs r3, #0
  1648. b LoopCopyDataInit
  1649. 80009bc: e002 b.n 80009c4 <LoopCopyDataInit>
  1650.  
  1651. 080009be <CopyDataInit>:
  1652.  
  1653. CopyDataInit:
  1654. ldr r4, [r2, r3]
  1655. 80009be: 58d4 ldr r4, [r2, r3]
  1656. str r4, [r0, r3]
  1657. 80009c0: 50c4 str r4, [r0, r3]
  1658. adds r3, r3, #4
  1659. 80009c2: 3304 adds r3, #4
  1660.  
  1661. 080009c4 <LoopCopyDataInit>:
  1662.  
  1663. LoopCopyDataInit:
  1664. adds r4, r0, r3
  1665. 80009c4: 18c4 adds r4, r0, r3
  1666. cmp r4, r1
  1667. 80009c6: 428c cmp r4, r1
  1668. bcc CopyDataInit
  1669. 80009c8: d3f9 bcc.n 80009be <CopyDataInit>
  1670.  
  1671. /* Zero fill the bss segment. */
  1672. ldr r2, =_sbss
  1673. 80009ca: 4a0a ldr r2, [pc, #40] @ (80009f4 <LoopForever+0x12>)
  1674. ldr r4, =_ebss
  1675. 80009cc: 4c0a ldr r4, [pc, #40] @ (80009f8 <LoopForever+0x16>)
  1676. movs r3, #0
  1677. 80009ce: 2300 movs r3, #0
  1678. b LoopFillZerobss
  1679. 80009d0: e001 b.n 80009d6 <LoopFillZerobss>
  1680.  
  1681. 080009d2 <FillZerobss>:
  1682.  
  1683. FillZerobss:
  1684. str r3, [r2]
  1685. 80009d2: 6013 str r3, [r2, #0]
  1686. adds r2, r2, #4
  1687. 80009d4: 3204 adds r2, #4
  1688.  
  1689. 080009d6 <LoopFillZerobss>:
  1690.  
  1691. LoopFillZerobss:
  1692. cmp r2, r4
  1693. 80009d6: 42a2 cmp r2, r4
  1694. bcc FillZerobss
  1695. 80009d8: d3fb bcc.n 80009d2 <FillZerobss>
  1696.  
  1697. /* Call static constructors */
  1698. bl __libc_init_array
  1699. 80009da: f000 f811 bl 8000a00 <__libc_init_array>
  1700. /* Call the application s entry point.*/
  1701. bl main
  1702. 80009de: f7ff fbf1 bl 80001c4 <main>
  1703.  
  1704. 080009e2 <LoopForever>:
  1705.  
  1706. LoopForever:
  1707. b LoopForever
  1708. 80009e2: e7fe b.n 80009e2 <LoopForever>
  1709. ldr r0, =_estack
  1710. 80009e4: 20009000 .word 0x20009000
  1711. ldr r0, =_sdata
  1712. 80009e8: 20000000 .word 0x20000000
  1713. ldr r1, =_edata
  1714. 80009ec: 20000004 .word 0x20000004
  1715. ldr r2, =_sidata
  1716. 80009f0: 08001158 .word 0x08001158
  1717. ldr r2, =_sbss
  1718. 80009f4: 20000004 .word 0x20000004
  1719. ldr r4, =_ebss
  1720. 80009f8: 200002b4 .word 0x200002b4
  1721.  
  1722. 080009fc <ADC1_IRQHandler>:
  1723. * @retval None
  1724. */
  1725. .section .text.Default_Handler,"ax",%progbits
  1726. Default_Handler:
  1727. Infinite_Loop:
  1728. b Infinite_Loop
  1729. 80009fc: e7fe b.n 80009fc <ADC1_IRQHandler>
  1730.  
  1731. 080009fe <SystemInit>:
  1732. {
  1733. /* Configure the Vector Table location -------------------------------------*/
  1734. #if defined(USER_VECT_TAB_ADDRESS)
  1735. SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
  1736. #endif /* USER_VECT_TAB_ADDRESS */
  1737. }
  1738. 80009fe: 4770 bx lr
  1739.  
  1740. 08000a00 <__libc_init_array>:
  1741. 8000a00: b570 push {r4, r5, r6, lr}
  1742. 8000a02: 4b0d ldr r3, [pc, #52] @ (8000a38 <__libc_init_array+0x38>)
  1743. 8000a04: 4d0d ldr r5, [pc, #52] @ (8000a3c <__libc_init_array+0x3c>)
  1744. 8000a06: 1b5e subs r6, r3, r5
  1745. 8000a08: 10b6 asrs r6, r6, #2
  1746. 8000a0a: 42ab cmp r3, r5
  1747. 8000a0c: d005 beq.n 8000a1a <__libc_init_array+0x1a>
  1748. 8000a0e: 2400 movs r4, #0
  1749. 8000a10: cd08 ldmia r5!, {r3}
  1750. 8000a12: 3401 adds r4, #1
  1751. 8000a14: 4798 blx r3
  1752. 8000a16: 42a6 cmp r6, r4
  1753. 8000a18: d8fa bhi.n 8000a10 <__libc_init_array+0x10>
  1754. 8000a1a: f000 f895 bl 8000b48 <_init>
  1755. 8000a1e: 4b08 ldr r3, [pc, #32] @ (8000a40 <__libc_init_array+0x40>)
  1756. 8000a20: 4d08 ldr r5, [pc, #32] @ (8000a44 <__libc_init_array+0x44>)
  1757. 8000a22: 1b5e subs r6, r3, r5
  1758. 8000a24: 10b6 asrs r6, r6, #2
  1759. 8000a26: 42ab cmp r3, r5
  1760. 8000a28: d005 beq.n 8000a36 <__libc_init_array+0x36>
  1761. 8000a2a: 2400 movs r4, #0
  1762. 8000a2c: cd08 ldmia r5!, {r3}
  1763. 8000a2e: 3401 adds r4, #1
  1764. 8000a30: 4798 blx r3
  1765. 8000a32: 42a6 cmp r6, r4
  1766. 8000a34: d8fa bhi.n 8000a2c <__libc_init_array+0x2c>
  1767. 8000a36: bd70 pop {r4, r5, r6, pc}
  1768. 8000a38: 0800114c .word 0x0800114c
  1769. 8000a3c: 0800114c .word 0x0800114c
  1770. 8000a40: 08001154 .word 0x08001154
  1771. 8000a44: 0800114c .word 0x0800114c
  1772.  
  1773. 08000a48 <__retarget_lock_acquire_recursive>:
  1774. 8000a48: 4770 bx lr
  1775. 8000a4a: 46c0 nop @ (mov r8, r8)
  1776.  
  1777. 08000a4c <__retarget_lock_release_recursive>:
  1778. 8000a4c: 4770 bx lr
  1779. 8000a4e: 46c0 nop @ (mov r8, r8)
  1780.  
  1781. 08000a50 <register_fini>:
  1782. 8000a50: 4b03 ldr r3, [pc, #12] @ (8000a60 <register_fini+0x10>)
  1783. 8000a52: b510 push {r4, lr}
  1784. 8000a54: 2b00 cmp r3, #0
  1785. 8000a56: d002 beq.n 8000a5e <register_fini+0xe>
  1786. 8000a58: 4802 ldr r0, [pc, #8] @ (8000a64 <register_fini+0x14>)
  1787. 8000a5a: f000 f805 bl 8000a68 <atexit>
  1788. 8000a5e: bd10 pop {r4, pc}
  1789. 8000a60: 00000000 .word 0x00000000
  1790. 8000a64: 08000a79 .word 0x08000a79
  1791.  
  1792. 08000a68 <atexit>:
  1793. 8000a68: b510 push {r4, lr}
  1794. 8000a6a: 0001 movs r1, r0
  1795. 8000a6c: 2300 movs r3, #0
  1796. 8000a6e: 2200 movs r2, #0
  1797. 8000a70: 2000 movs r0, #0
  1798. 8000a72: f000 f815 bl 8000aa0 <__register_exitproc>
  1799. 8000a76: bd10 pop {r4, pc}
  1800.  
  1801. 08000a78 <__libc_fini_array>:
  1802. 8000a78: b570 push {r4, r5, r6, lr}
  1803. 8000a7a: 4c07 ldr r4, [pc, #28] @ (8000a98 <__libc_fini_array+0x20>)
  1804. 8000a7c: 4d07 ldr r5, [pc, #28] @ (8000a9c <__libc_fini_array+0x24>)
  1805. 8000a7e: 1b64 subs r4, r4, r5
  1806. 8000a80: 10a4 asrs r4, r4, #2
  1807. 8000a82: d005 beq.n 8000a90 <__libc_fini_array+0x18>
  1808. 8000a84: 3c01 subs r4, #1
  1809. 8000a86: 00a3 lsls r3, r4, #2
  1810. 8000a88: 58eb ldr r3, [r5, r3]
  1811. 8000a8a: 4798 blx r3
  1812. 8000a8c: 2c00 cmp r4, #0
  1813. 8000a8e: d1f9 bne.n 8000a84 <__libc_fini_array+0xc>
  1814. 8000a90: f000 f860 bl 8000b54 <_fini>
  1815. 8000a94: bd70 pop {r4, r5, r6, pc}
  1816. 8000a96: 46c0 nop @ (mov r8, r8)
  1817. 8000a98: 08001158 .word 0x08001158
  1818. 8000a9c: 08001154 .word 0x08001154
  1819.  
  1820. 08000aa0 <__register_exitproc>:
  1821. 8000aa0: b5f0 push {r4, r5, r6, r7, lr}
  1822. 8000aa2: 46d6 mov lr, sl
  1823. 8000aa4: 464f mov r7, r9
  1824. 8000aa6: 4646 mov r6, r8
  1825. 8000aa8: 4698 mov r8, r3
  1826. 8000aaa: 4b24 ldr r3, [pc, #144] @ (8000b3c <__register_exitproc+0x9c>)
  1827. 8000aac: b5c0 push {r6, r7, lr}
  1828. 8000aae: 0006 movs r6, r0
  1829. 8000ab0: 6818 ldr r0, [r3, #0]
  1830. 8000ab2: 469a mov sl, r3
  1831. 8000ab4: 000f movs r7, r1
  1832. 8000ab6: 4691 mov r9, r2
  1833. 8000ab8: f7ff ffc6 bl 8000a48 <__retarget_lock_acquire_recursive>
  1834. 8000abc: 4b20 ldr r3, [pc, #128] @ (8000b40 <__register_exitproc+0xa0>)
  1835. 8000abe: 681d ldr r5, [r3, #0]
  1836. 8000ac0: 2d00 cmp r5, #0
  1837. 8000ac2: d032 beq.n 8000b2a <__register_exitproc+0x8a>
  1838. 8000ac4: 4653 mov r3, sl
  1839. 8000ac6: 686c ldr r4, [r5, #4]
  1840. 8000ac8: 6818 ldr r0, [r3, #0]
  1841. 8000aca: 2c1f cmp r4, #31
  1842. 8000acc: dc30 bgt.n 8000b30 <__register_exitproc+0x90>
  1843. 8000ace: 2e00 cmp r6, #0
  1844. 8000ad0: d10c bne.n 8000aec <__register_exitproc+0x4c>
  1845. 8000ad2: 1c63 adds r3, r4, #1
  1846. 8000ad4: 3402 adds r4, #2
  1847. 8000ad6: 00a4 lsls r4, r4, #2
  1848. 8000ad8: 606b str r3, [r5, #4]
  1849. 8000ada: 5167 str r7, [r4, r5]
  1850. 8000adc: f7ff ffb6 bl 8000a4c <__retarget_lock_release_recursive>
  1851. 8000ae0: 2000 movs r0, #0
  1852. 8000ae2: bce0 pop {r5, r6, r7}
  1853. 8000ae4: 46ba mov sl, r7
  1854. 8000ae6: 46b1 mov r9, r6
  1855. 8000ae8: 46a8 mov r8, r5
  1856. 8000aea: bdf0 pop {r4, r5, r6, r7, pc}
  1857. 8000aec: 4649 mov r1, r9
  1858. 8000aee: 2288 movs r2, #136 @ 0x88
  1859. 8000af0: 00a3 lsls r3, r4, #2
  1860. 8000af2: 18eb adds r3, r5, r3
  1861. 8000af4: 5099 str r1, [r3, r2]
  1862. 8000af6: 21c4 movs r1, #196 @ 0xc4
  1863. 8000af8: 0049 lsls r1, r1, #1
  1864. 8000afa: 468c mov ip, r1
  1865. 8000afc: 44ac add ip, r5
  1866. 8000afe: 4661 mov r1, ip
  1867. 8000b00: 3a87 subs r2, #135 @ 0x87
  1868. 8000b02: 40a2 lsls r2, r4
  1869. 8000b04: 6809 ldr r1, [r1, #0]
  1870. 8000b06: 4691 mov r9, r2
  1871. 8000b08: 4311 orrs r1, r2
  1872. 8000b0a: 4662 mov r2, ip
  1873. 8000b0c: 6011 str r1, [r2, #0]
  1874. 8000b0e: 2184 movs r1, #132 @ 0x84
  1875. 8000b10: 4642 mov r2, r8
  1876. 8000b12: 0049 lsls r1, r1, #1
  1877. 8000b14: 505a str r2, [r3, r1]
  1878. 8000b16: 2e02 cmp r6, #2
  1879. 8000b18: d1db bne.n 8000ad2 <__register_exitproc+0x32>
  1880. 8000b1a: 0029 movs r1, r5
  1881. 8000b1c: 464a mov r2, r9
  1882. 8000b1e: 318d adds r1, #141 @ 0x8d
  1883. 8000b20: 31ff adds r1, #255 @ 0xff
  1884. 8000b22: 680b ldr r3, [r1, #0]
  1885. 8000b24: 4313 orrs r3, r2
  1886. 8000b26: 600b str r3, [r1, #0]
  1887. 8000b28: e7d3 b.n 8000ad2 <__register_exitproc+0x32>
  1888. 8000b2a: 4d06 ldr r5, [pc, #24] @ (8000b44 <__register_exitproc+0xa4>)
  1889. 8000b2c: 601d str r5, [r3, #0]
  1890. 8000b2e: e7c9 b.n 8000ac4 <__register_exitproc+0x24>
  1891. 8000b30: f7ff ff8c bl 8000a4c <__retarget_lock_release_recursive>
  1892. 8000b34: 2001 movs r0, #1
  1893. 8000b36: 4240 negs r0, r0
  1894. 8000b38: e7d3 b.n 8000ae2 <__register_exitproc+0x42>
  1895. 8000b3a: 46c0 nop @ (mov r8, r8)
  1896. 8000b3c: 20000000 .word 0x20000000
  1897. 8000b40: 20000120 .word 0x20000120
  1898. 8000b44: 20000124 .word 0x20000124
  1899.  
  1900. 08000b48 <_init>:
  1901. 8000b48: b5f8 push {r3, r4, r5, r6, r7, lr}
  1902. 8000b4a: 46c0 nop @ (mov r8, r8)
  1903. 8000b4c: bcf8 pop {r3, r4, r5, r6, r7}
  1904. 8000b4e: bc08 pop {r3}
  1905. 8000b50: 469e mov lr, r3
  1906. 8000b52: 4770 bx lr
  1907.  
  1908. 08000b54 <_fini>:
  1909. 8000b54: b5f8 push {r3, r4, r5, r6, r7, lr}
  1910. 8000b56: 46c0 nop @ (mov r8, r8)
  1911. 8000b58: bcf8 pop {r3, r4, r5, r6, r7}
  1912. 8000b5a: bc08 pop {r3}
  1913. 8000b5c: 469e mov lr, r3
  1914. 8000b5e: 4770 bx lr
  1915.  
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