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Briotar

log_&

Apr 17th, 2021
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VHDL 0.28 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3.  
  4. entity \log_&\ is
  5.      port(
  6.          A : in STD_LOGIC;
  7.          B : in STD_LOGIC;
  8.          C : in STD_LOGIC;
  9.          Y : out STD_LOGIC
  10.          );
  11. end \log_&\;
  12.  
  13. architecture \log_&\ of \log_&\ is
  14. begin
  15.  
  16.         Y <= not(A and B and C) after 1ns;
  17.  
  18. end \log_&\;
  19.  
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