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- library IEEE;
- use IEEE.std_logic_1164.all;
- entity \log_&\ is
- port(
- A : in STD_LOGIC;
- B : in STD_LOGIC;
- C : in STD_LOGIC;
- Y : out STD_LOGIC
- );
- end \log_&\;
- architecture \log_&\ of \log_&\ is
- begin
- Y <= not(A and B and C) after 1ns;
- end \log_&\;
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