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- library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.numeric_std.ALL;
- use STD.textio.all;
- use IEEE.std_logic_textio.ALL;
- entity testbench is
- end entity;
- architecture test of testbench is
- signal EndOfSim : boolean := false;
- constant half_clk : time := 10 ps;
- type frame_size_array is array (0 to 1) of integer;
- constant frame_size : frame_size_array := (0 => 64800, 1 => 16200);
- constant address_space : frame_size_array := (0 => 64800, 1 => 16200);
- constant input_size : integer := 1;
- signal i_clk : std_logic := '0';
- signal i_enb : std_logic := '0';
- signal i_res : std_logic := '0';
- signal i_frame_select : std_logic_vector (0 downto 0);
- signal i_QAM_select : std_logic_vector (2 downto 0);
- signal i_data : std_logic_vector (input_size - 1 downto 0);
- signal o_data : std_logic_vector (input_size - 1 downto 0);
- signal expected : std_logic_vector (input_size - 1 downto 0);
- signal start_r : std_logic;
- signal correct : std_logic;
- file testing_data : text;
- component clk_dvb_s2x
- Port(
- i_clk : in std_logic;
- i_res : in std_logic;
- i_enb : in std_logic;
- i_QAM_select : in std_logic_vector (2 downto 0);
- i_frame_select : in std_logic_vector (0 downto 0);
- i_data : in std_logic_vector (0 downto 0);
- o_data : out std_logic_vector (0 downto 0));
- end component;
- begin
- dut: clk_dvb_s2x
- port map(
- i_clk => i_clk,
- i_enb => i_enb,
- i_res => i_res,
- i_data => i_data,
- o_data => o_data,
- i_frame_select => i_frame_select,
- i_QAM_select => i_QAM_select);
- clock: process is
- begin -- clock generator, toggle clk every half periode
- if EndOfSim then
- wait;
- end if;
- i_clk <= not i_clk;
- wait for half_clk;
- end process;
- main: process is
- variable read_line : line;
- variable frame_count : integer;
- variable M_frame_select : std_logic_vector (0 downto 0);
- variable int_frame_select : integer;
- variable M_APSK_SELECT : std_logic_vector (2 downto 0);
- variable M_INPUT : std_logic_vector (0 to frame_size(0) - 1);
- variable M_OUTPUT : std_logic_vector (0 to frame_size(0) - 1);
- variable frame_counter : integer;
- variable input_counter : integer;
- variable input : std_logic_vector (input_size - 1 downto 0);
- variable output : std_logic_vector (input_size - 1 downto 0);
- variable lower_bound : integer;
- variable upper_bound : integer;
- begin
- file_open(testing_data, "Test_input_interleaver.txt", read_mode);
- readline(testing_data, read_line);
- read(read_line, frame_count);
- read(read_line, M_frame_select);
- int_frame_select := to_integer(unsigned(M_frame_select));
- report "frame_count = " & integer'image(frame_count);
- wait until falling_edge(i_clk);
- i_enb <= '0';
- i_res <= '1';
- i_frame_select <= M_frame_select;
- wait until rising_edge(i_clk);
- wait until falling_edge(i_clk);
- i_enb <= '1';
- i_res <= '0';
- frame_counter := 0;
- -- FIRST LOOP THAT WRITES WORDS
- while frame_counter < frame_count + 1 loop
- if (frame_counter < frame_count) then
- readline(testing_data, read_line);
- read(read_line, M_APSK_SELECT);
- read(read_line, M_INPUT(0 to frame_size(int_frame_select)-1));
- report "Frame: " & integer'image(frame_counter) & " M_APSK_SELECT = " & integer'image(to_integer(unsigned(M_APSK_SELECT)));
- else end if;
- -- SECOND LOOP THAT WRITES WORDS
- input_counter := 0;
- while input_counter < (address_space(int_frame_select)) loop
- lower_bound := input_size * input_counter;
- upper_bound := input_size * (input_counter + 1) - 1;
- -- WRITE INPUT(DON'T WRITE AT THE END)
- if(frame_counter < frame_count) then
- i_QAM_select <= M_APSK_SELECT;
- i_data <= M_INPUT(lower_bound to upper_bound);
- else
- i_data <= (others => 'U');
- end if;
- wait until rising_edge(i_clk);
- -- WRITE EXPECTED OUTPUT(DON'T WRITE AT THE BEGINNING)
- if (frame_counter > 0) then
- expected <= M_OUTPUT(lower_bound to upper_bound);
- else end if;
- wait until falling_edge(i_clk);
- input_counter := input_counter + 1;
- end loop;
- if (frame_counter < frame_count) then
- read (read_line, M_OUTPUT(0 to frame_size(int_frame_select)-1));
- else end if;
- start_r <= '1';
- frame_counter := frame_counter + 1;
- end loop;
- file_close(testing_data);
- start_r <= '0';
- i_enb <= '0';
- wait for 10*half_clk;
- EndOfSim <= true;
- report "Simulation finished succcesfully" severity FAILURE;
- wait;
- end process;
- testing: process is
- begin
- wait until falling_edge(i_clk);
- if(start_r = '1') then
- if(expected = o_data) then
- correct <= '1';
- else
- report "ERROR: incorrect";
- wait for 4*half_clk;
- report "ERROR: exiting" severity FAILURE;
- correct <= '0';
- end if;
- end if;
- end process;
- end architecture;
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