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- library ieee;
- use ieee.std_logic_1164.all; -- uzycie standardu bibliotek
- use ieee.std_logic_unsigned.all;
- entity kolokwium1 is -- deklaracja jednostki
- port
- (
- i1, i2, i3, i4: in std_logic;
- x: inout std_logic; -- standard logic bierze sie z biblioteki`
- reset: in std_logic;
- key: in std_logic; -- 'in' deklaracja na wejsciu
- ledg: out std_logic; -- 'out' deklaracja na wyjsciu
- ledr: out std_logic_vector(2 downto 0) --w ostatnej deklaracji nie ma srednika
- ); -- to ostatni srednik
- end entity;
- architecture dzialani_od_kolokwium of kolokwium1 is --czesc deklaracji : np. typow, sygnalow, stalych, podprogramy, komponenty
- type State_type is (A,B,C);
- signal ST: State_type;
- begin -- tutaj definicja dzialania modulu, czesc opisowa : np petle i warunki
- x <= (i1 and (not i2) and i4) or (i2 and i1 (not i3 )) or (not i4);
- process (reset, key, x)
- begin
- if (reset='1') then
- ST <= A; --<=wektor
- elsif ( key'event and key='1') then
- case ST is
- when A =>
- ledr (2 downto 0) <= "001";
- if (x= '1' ) then
- ST <= C;
- ledg<='1';
- else
- ST <= B;
- ledg <='0';
- end if;
- when B =>
- ledr (2 downto 0) <= "010";
- if (x='1') then
- ST <= A;
- ledg<='1';
- else
- ST <= C;
- ledg <='0';
- end if;
- when C =>
- ledr (2 downto 0) <= "010";
- if (x='1') then
- ST <= A;
- ledg<='1';
- else
- ST <= B;
- ledg <= '0';
- end if;
- end case;
- end if;
- end process;
- end architecture;
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