Device PPI

module device(address, GNT, CLK, force_req, addressToContact, RESET, REQ, Frame,AD, C_BE, IReady, TReady, DevSel);
    input GNT, CLK, RESET, force_req;
    input [31:0] address, addressToContact;

    output REQ;

    inout [31:0] AD;
    input [3:0] C_BE;
    inout Frame, IReady, TReady, DevSel;

    reg [31:0] mem [9:0];
    wire [31:0] data [2:0]; //contains AA

    integer i = 0;
    integer numberOfTransactions;

    wire [1:0]phasesWire;
    reg [1:0]numberOfPhases;

    integer posEdge = 0;

    assign data[0] = 32'hAA_AA_AA_AA;
    assign data[1] = 32'hBB_BB_BB_BB;
    assign data[2] = 32'hCC_CC_CC_CC;
    assign phasesWire= (address == 0 && addressToContact == 1)? 3 : (address == 0 && addressToContact == 2) ? 2 :(address == 1)? 2:(address==2)? 1 :0;
    reg isData;

    reg isMaster;

    reg REQ_reg;
    assign REQ = REQ_reg;

    reg Frame_reg;
    reg [31:0] AD_reg;
    assign Frame = (isMaster) ? Frame_reg : 1'bz;
    assign AD = (isMaster) ? AD_reg : 1'bz;

    always @(CLK)
    begin
    posEdge = ~posEdge;
        if (posEdge)
        begin
            if (!force_req)
            begin
                i = i+1;
                REQ_reg = 0;
            end

            else if (i != 0)
            begin
                numberOfTransactions = i; //
                i = 0;
            end

            else
                i = 0;

            if (GNT == 0 && Frame && IReady) //bus granted and bus is idle
            begin

                isMaster = 1;
                isData=0;
                numberOfPhases<=phasesWire;
            end

            else if (isMaster) // not first cycle
            begin

            end
        end
        else
        begin
            if(isMaster)
        begin
            Frame_reg = 0;
            if(!isData)
                begin
            AD_reg = addressToContact;
            isData=1;
            end
            else

            if(numberOfPhases>0)
            begin
                numberOfPhases = numberOfPhases - 1;
                AD_reg = data[address];
                if(numberOfPhases ==0)
                    begin
                        Frame_reg = 1;
                        //isMaster=0;
                    end
            end
            else
                isMaster=0;
    end
        end
    end
endmodule