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symonhasan

1:8 Demux

Feb 4th, 2020
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  1. module demux( in , s0 , s1 , s2 , d0 , d1 , d2 , d3 , d4 , d5 , d6, d7 );
  2.     input in , s0 , s1, s2;
  3.     output d0 , d1 , d2 , d3 , d4 , d5 , d6 , d7;
  4.     assign d0 = ( in & ~s2 & ( ~s1 & ~s0 ) ),
  5.         d1 = ( in & ~s2 & ( ~s1 & s0 ) ),
  6.         d2 = ( in & ~s2 & ( s1 & ~s0 ) ),
  7.         d3 = ( in & ~s2 & ( s1 & s0 ) ),
  8.         d4 = ( in & s2 & ( ~s1 & ~s0 ) ),
  9.         d5 = ( in & s2 & ( ~s1 & s0 ) ),
  10.         d6 = ( in & s2 & ( s1 & ~s0 ) ),
  11.         d7 = ( in & s2 & ( s1 & s0 ) );
  12. endmodule
  13. module Test;
  14.     reg in , s0 , s1 , s2;
  15.     wire d0 , d1 , d2 , d3 , d4 , d5 , d6 , d7;
  16.    
  17.     demux uut(
  18.         .in( in ),
  19.         .s0( s0 ),
  20.         .s1( s1 ),
  21.         .s2( s2 ),
  22.         .d0( d0 ),
  23.         .d1( d1 ),
  24.         .d2( d2 ),
  25.         .d3( d3 ),
  26.         .d4( d4 ),
  27.         .d5( d5 ),
  28.         .d6( d6 ),
  29.         .d7( d7 )  
  30.     );
  31.     initial begin
  32.        // $dumpfile("adder4bit.vcd");
  33.         //$dumpvars(0,adder4b_test);
  34.        
  35.        
  36.         in = 1; s2 = 0; s1 = 0; s0 = 0;
  37.         #10;
  38.         in = 1; s2 = 0; s1 = 0; s0 = 1;  
  39.         #10;
  40.         in = 1; s2 = 0; s1 = 1; s0 = 0;
  41.         #10;
  42.         in = 1; s2 = 0; s1 = 1; s0 = 1;  
  43.         #10;
  44.         in = 1; s2 = 1; s1 = 0; s0 = 0;
  45.         #10;
  46.         in = 1; s2 = 1; s1 = 0; s0 = 1;  
  47.         #10;
  48.         in = 1; s2 = 1; s1 = 1; s0 = 0;
  49.         #10;
  50.         in = 1; s2 = 1; s1 = 1; s0 = 1;  
  51.         #10;
  52.     end
  53.    
  54.     initial begin
  55.           $monitor("Output -> %b%b%b%b%b%b%b%b\n",d7,d6,d5,d4,d3,d2,d1,d0);
  56.          end  
  57. endmodule
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