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- module demux( in , s0 , s1 , s2 , d0 , d1 , d2 , d3 , d4 , d5 , d6, d7 );
- input in , s0 , s1, s2;
- output d0 , d1 , d2 , d3 , d4 , d5 , d6 , d7;
- assign d0 = ( in & ~s2 & ( ~s1 & ~s0 ) ),
- d1 = ( in & ~s2 & ( ~s1 & s0 ) ),
- d2 = ( in & ~s2 & ( s1 & ~s0 ) ),
- d3 = ( in & ~s2 & ( s1 & s0 ) ),
- d4 = ( in & s2 & ( ~s1 & ~s0 ) ),
- d5 = ( in & s2 & ( ~s1 & s0 ) ),
- d6 = ( in & s2 & ( s1 & ~s0 ) ),
- d7 = ( in & s2 & ( s1 & s0 ) );
- endmodule
- module Test;
- reg in , s0 , s1 , s2;
- wire d0 , d1 , d2 , d3 , d4 , d5 , d6 , d7;
- demux uut(
- .in( in ),
- .s0( s0 ),
- .s1( s1 ),
- .s2( s2 ),
- .d0( d0 ),
- .d1( d1 ),
- .d2( d2 ),
- .d3( d3 ),
- .d4( d4 ),
- .d5( d5 ),
- .d6( d6 ),
- .d7( d7 )
- );
- initial begin
- // $dumpfile("adder4bit.vcd");
- //$dumpvars(0,adder4b_test);
- in = 1; s2 = 0; s1 = 0; s0 = 0;
- #10;
- in = 1; s2 = 0; s1 = 0; s0 = 1;
- #10;
- in = 1; s2 = 0; s1 = 1; s0 = 0;
- #10;
- in = 1; s2 = 0; s1 = 1; s0 = 1;
- #10;
- in = 1; s2 = 1; s1 = 0; s0 = 0;
- #10;
- in = 1; s2 = 1; s1 = 0; s0 = 1;
- #10;
- in = 1; s2 = 1; s1 = 1; s0 = 0;
- #10;
- in = 1; s2 = 1; s1 = 1; s0 = 1;
- #10;
- end
- initial begin
- $monitor("Output -> %b%b%b%b%b%b%b%b\n",d7,d6,d5,d4,d3,d2,d1,d0);
- end
- endmodule
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