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cstart.S Cortex-A8

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  1. /*
  2. * cstart.S
  3. *
  4.  *  Initial code to get Neutrino started
  5. *
  6. * This code runs as the first instructions after control has transferred
  7. * from any bootup monitor.  This module defines a minimal bootup stack,
  8. * and sets SP to this stack, and then starts running C code in _main().
  9. */
  10.  
  11.     .data
  12.     .globl  stack
  13.     .globl  boot_args
  14.     .globl  vstart
  15.    
  16. boot_args:
  17.     .ascii  "ddpvbskr"  /* signature for mkifs */
  18. stack_end:
  19.     .space  3*1024
  20. stack:
  21.     .text
  22.  
  23.     .extern _main
  24.     .globl  _start
  25.  
  26. _start:
  27.  
  28.     //
  29.     // Turn off interrupts and make sure we are in SVC mode
  30.     //
  31.     mrs     lr, cpsr
  32.     bic     lr, lr, #0x1f
  33.     orr     lr, lr, #0xd3
  34.     msr     cpsr, lr
  35.  
  36.     //
  37.     // Turn off MMU and data cache if necessary.
  38.     // WARNING: assumes we are running with a 1-1 mapping if MMU is enabled.
  39.     //
  40.     mrc     p15, 0, lr, c1, c0, 0
  41.     bic     lr, lr, #0x0000000f         // WCAM bits
  42.     bic     lr, lr, #0x00000300         // RS   bits
  43.     mcr     p15, 0, lr, c1, c0, 0
  44.     mov     r0, #0
  45.     mov     r0, r0
  46.     mov     r0, r0
  47.  
  48.     //
  49.     // Set the translation table base
  50.     //
  51.     ldr     r0, =_arm_board_ttb         // set start of Translation Table base
  52.     orr     r0, r0, #((3 << 3) | 3)
  53.     mcr     p15, 0, r0, c2, c0, 0
  54. #   mcr     p15, 0, r0, c2, c0, 1       // set TTBR1 so armv_setup_v7 works
  55.  
  56.  
  57.  
  58.     /* Enable the MMU, I-Cache and D-Cache */
  59.     mrc     p15, 0, r0, c1, c0, 0
  60.     BIC     r0, r0, #(1 << 12)          // enable I Cache
  61.     BIC     r0, r0, #(1 <<  2)          // enable D Cache
  62.     BIC     r0, r0, #(1 <<  0)          // enable MMU
  63.     mcr     p15, 0, r0, c1, c0, 0
  64.  
  65.  
  66.  
  67.  
  68.     ldr     sp, =stack
  69.     bl      _main
  70.  
  71.  
  72.  
  73. oops:
  74.     b       oops
  75.  
  76. /*
  77.  * void vstart(uintptr_t syspageptr, unsigned entry_point, unsigned cpunum)
  78. *
  79. * Enable the mmu and jump to the next program's entry point
  80. * The next program is responsible for tearing down the 1-1 section
  81. * mapping of the startup program set up by init_mmu().
  82. */
  83. vstart:
  84.  
  85.     /* SAVE CONTEXT OF REGISTERS */
  86.     mov     r4, r1
  87.     mov     r5, r2
  88.  
  89.  
  90.  
  91.     //
  92.    // Invalidate L1 I/D
  93.    //
  94.     mcr p15, 0, ip, c8, c7, 0   // Invalidate entire unified TLB
  95.     mcr p15, 0, ip, c8, c6, 0   // Invalidate entire data TLB
  96.     mcr p15, 0, ip, c8, c5, 0   // Invalidate entire instruction TLB
  97.     dsb
  98.     isb
  99.     mcr     p15, 0, ip, c7, c5, 0   // invalidate icache
  100.     mcr     p15, 0, ip, c7, c5, 6  // invalidate BP array
  101.     dsb
  102.     isb
  103.  
  104.  
  105.     //
  106.     // Fluch D-cache
  107.     //
  108.     bl      _armv7_flush_whole_dcache
  109.  
  110.     /*
  111.     * Set the translation table base
  112.     */
  113.     ldr     ip, =L1_paddr
  114.     ldr     ip, [ip]
  115.     add     ip, ip, r5, lsl #14         // L1_paddr * (cpu * ARM_L1_SIZE)
  116.     mcr     p15, 0, ip, c2, c0, 0       // TTBR0
  117.     mcr     p15, 0, ip, c2, c0, 1       // TTBR1
  118.     mov     ip, #1
  119.     mcr     p15, 0, ip, c2, c0, 2       // TTBCR = 1
  120.  
  121.     /*
  122.     * Enable MMU domain 0
  123.     */
  124.     mov     ip, #1
  125.     mcr     p15, 0, ip, c3, c0, 0
  126.  
  127.     /*
  128.     * Enable the MMU, using read-modify-write to preserve reserved bits.
  129.     */
  130.     ldr     r2, =mmu_cr_clr
  131.     ldr     r3, =mmu_cr_set
  132.     ldr     r2, [r2]
  133.     ldr     r3, [r3]
  134.     mrc     p15, 0, lr, c1, c0, 0
  135.     bic     ip, lr, r2
  136.     orr     ip, ip, r3
  137.     dsb
  138.     isb
  139.     mcr     p15, 0, ip, c1, c0, 0
  140.     dsb
  141.     isb
  142.     mov     ip, #0
  143.  
  144.     /*
  145.     * Invalidate the caches and TLBs
  146.     */
  147.    .align 5
  148.     mcr     p15, 0, ip, c7, c5, 0   // invalidate instruction caches
  149.     mcr     p15, 0, ip, c8, c7, 0   // invalidate TLBs
  150.     dsb
  151.     isb
  152.  
  153.     /*
  154.     * Call entry_point(_syspage_ptr, cpunum)
  155.     */
  156.    /* RESTORE CONTEXT OF REGISTERS */
  157.     mov     r1, r5
  158.     mov     pc, r4
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