ADLD_T1_Q3

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    12:37:12 07/23/2021
// Design Name:
// Module Name:    mc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mc(input clk, output reg c1, output reg c2
    );

     reg x1,x2,y1,y2;

     always@(posedge clk) begin

     x1 = x1 + 1;
     x2 = x2 + 1;
     y1 = y1 + 1;
     y2 = y2 + 1;

     if (x1 == 6) begin
     c1 = 1'b1;
     x1 = 1;
     end

     if (x2 == 6) begin
     c1 = 0;
     x2 = 1;
     end

     if (y1 == 6) begin
     c2 = 1'b1;
     y1 = 1;
     end

     if (y2 == 7) begin
     c2 = 0;
     y2 = 1;
     end

     end

     initial begin
     x1 = 1;
     x2 = 3;
     y1 = 1;
     y2 = 5;
     c1 = 1'b1;
     c2 = 1'b1;
     end


endmodule