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Shaco74

Untitled

Jan 9th, 2022 (edited)
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity akkumulator is
  6.  
  7. port (
  8. d  : in std_logic_vector(3 downto 0); -- Daten-Eingang
  9.       ld : in std_logic; -- MUX Steuereingang: 0(gedrückt)=Ergebnis durchschalten, 1(nicht gedrückt)= Dateneingang durchschalten
  10. sub : in std_logic; -- 0=+, 1=-
  11. e  : in std_logic; -- enable Auffangregister 0(gedrückt)= enabled
  12. clk : in std_logic; -- Takt
  13.  
  14. c : out std_logic; -- LEDG(4) carry out
  15. q : out std_logic_vector(3 downto 0); -- LEDG(3..0) Daten-Ausgang
  16. -- debug pins:
  17. z_out : out std_logic_vector(4 downto 0)
  18. -- LEDR(4..0), z4 = carry
  19. );
  20. end entity akkumulator;
  21.  
  22. architecture akk of akkumulator is
  23.  
  24. signal q_out,q_in: std_logic_vector(4 downto 0);
  25. signal x,y,yu,yui: std_logic_vector(3 downto 0);
  26. signal z: std_logic_vector(4 downto 0);
  27.  
  28. begin
  29.  
  30.     y <= d;
  31.  
  32.  
  33.     with ld select --Multiplexer
  34.         q_in <=  z when '0',
  35.         std_logic_vector('0' & signed(d)) when '1';
  36.  
  37.  
  38.     x <= q_out(3 downto 0);
  39.  
  40.     yu <=  y xor "1111";
  41.     yui <= std_logic_vector(signed(yu) + 1);
  42.  
  43.     with sub select --Rechner
  44.         z  <= std_logic_vector(signed('0' & x)+ signed('0' & y)) when '0',
  45.         std_logic_vector(signed('0' & x)+ signed('0' & yui)) when '1';
  46.  
  47.     z_out <= z;
  48.    
  49.     P: process (clk)
  50.     begin
  51.  
  52.         if rising_edge(clk) then
  53.         if e = '1' then
  54.         q_out  <= q_in;
  55.         end if;
  56.         end if;
  57.  
  58.         q <=  q_out(3 downto 0);
  59.         c <= q_out(4);
  60.  
  61.     end process ;
  62.  
  63. end architecture akk;
  64.  
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