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- // -------------------------------------------------------------------------------------
- // Question 2
- // -------------------------------------------------------------------------------------
- module Question_2 #(parameter width = 8)
- (
- // Inputs
- input logic [17:0] SW, // Switches
- input logic [3:0] KEY, // Push Buttons
- input logic CLOCK_27, // Clock
- input logic CLOCK_50, // Clock
- // Outputs
- output logic [6:0] HEX0, // SSD 0
- HEX1, // SSD 1
- HEX2, // SSD 2
- HEX3, // SSD 3
- HEX4, // SSD 4
- HEX5, // SSD 5
- HEX6, // SSD 6
- HEX7, // SSD 7
- output logic [17:0] LEDR, // Red LEDS
- output logic [8:0] LEDG // Green LEDS
- );
- // Internal Logic
- logic [width-1:0] A,
- B,
- B_sign_out,
- C,
- AU_XNOR_out,
- AU_XOR_out,
- LO_AND_out,
- LO_OR_out,
- LO_XOR_out,
- LO_NOR_out,
- AU_out,
- LO_out,
- LO_1,
- LO_2,
- LO_3,
- ALU_out;
- logic [3:0] F;
- logic Cout,
- OVs,
- OVu,
- OV;
- // Assigning Numbers A and B to the Inputs Switches
- assign A = SW[15:8];
- assign B = SW[7:0];
- assign F = KEY[3:0];
- // Displaying the Inputs
- disp_8b_SSD disp_A(A[width-1:0], HEX6[6:0], HEX7[6:0]);
- disp_8b_SSD disp_B(B[width-1:0], HEX4[6:0], HEX5[6:0]);
- // ---- Add/Subtract Hardware with Overflow Detection ----
- // AU - Choose between Add and Sub Mode
- parameterized_2_1_MUX #(width) mux1(B[width-1:0], ~(B[width-1:0]), F[1], B_sign_out[width-1:0]);
- // AU - Adding A and (-)B
- adder_12_bit(A[width-1:0], mux_1_out[width-1:0], F[1], C[width-1:0], Cout);
- // AU - Top XNOR
- assign AU_XNOR_out[width-1:0] = B_sign_out[width-1:0] ~^ A[width-1:0];
- // AU - Top XOR
- assign AU_XOR_out[width-1:0] = A[width-1:0] ^ C[width-1:0];
- // AU - OVs
- assign OVs = AU_XNOR_out[width-1:0] & AU_XOR_out[width-1:0]; // NEED TO CHECK WHETHER OVs IS N-BIT OR 1 BIT
- // AU - OVu
- assign OVu = Cout ^ F[1];
- // AU - Overall Overflow OV
- parameterized_2_1_MUX #(width) mux2(OVs, OVu, F[0], OV);
- // Turning on LED is OV is detected
- assign LEDR[0] = OV;
- // ---- SLT Logic ----
- // AU - LO_1
- parameterized_2_1_MUX #(width) mux3(C[width-1:0], Cout, OVs, LO_1);
- // AU - LO_2
- parameterized_2_1_MUX #(width) mux4(LO_1[width-1:0], ~Cout, F[0], LO_2[width-1:0]);
- // AU - LO_3 - Zero Extension
- // TODO
- // AU - LO_3
- parameterized_2_1_MUX #(width) mux5(LO_3[width-1:0], C[width-1:0], ~F[2], AU_out[width-1:0]);
- // LO - AND
- assign LO_AND_out[width-1:0] = A[width-1:0] & B[width-1:0];
- // LO - OR
- assign LO_OR_out[width-1:0] = A[width-1:0] | B[width-1:0];
- // LO - XOR
- assign LO_XOR_out[width-1:0] = A[width-1:0] ^ B[width-1:0];
- // LO - NOR
- assign LO_NOR_out[width-1:0] = A[width-1:0] ~| B[width-1:0];
- // LO - LO_out
- parameterized_4_1_MUX #(width) mux6(LO_AND_out[width-1:0], LO_OR_out[width-1:0], LO_XOR_out[width-1:0], LO_NOR_out[width-1:0], F[1:0], LO_out[width-1:0]);
- // ALU_out
- parameterized_2_1_MUX #(width) mux7(ALU_out[width-1:0], LO_out[width-1:0], F[2], ALU_out[width-1:0]);
- // ---- Displaying the Result ----
- disp_equals_sign(HEX3[6:0]);
- display_8b_with_Cout disp_ALU_out(ALU_out[width-1:0], Cout, HEX0[6:0], HEX1[6:0], HEX2[6:0]);
- endmodule
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