LK

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lyskryss is
  port(
    CLOCK_50 : in    std_logic;
    KEY      : in    std_logic_vector(3 downto 0);
    SW       : in    std_logic_vector(17 downto 0);
    GPIO     : inout std_logic_vector(35 downto 0);
    LEDR     : out   std_logic_vector(17 downto 0)
    );
end entity lyskryss;



architecture RTL of lyskryss is

  signal reset_n, clk, Enable, hallo : std_logic;
  signal velg_enable                 : std_logic_vector(2 downto 0);
  signal state_output                : std_logic_vector(5 downto 0);
  type tilstand is (fase1, fase2, fase3, fase4, fase5, fase6);
  signal state                       : tilstand;
  type ROM_array is array (0 to 5) of std_logic_vector(5 downto 0);
  -- 000001 OV-GRONN / 000010 OV-GUL / 000100 OV-ROD / 001000 NS-GRONN
  -- 010000 NS-gul / 100000 NS-ROD
  constant ROM_fase                  : ROM_array := ("001100", "010100", "100110", "100001", "100010", "110100");
  type tid_array is array (0 to 5) of integer range 0 to 127;
  constant fase_tid                  : tid_array := (40, 4, 3, 40, 4, 3);
  signal teller                      : integer range 0 to 41;
--  signal Sensor1N, Sensor1S, Sensor2O, Sensor2V : std_logic;

  component reset_sync is
    port(
      clk       : in  std_logic;
      rst_n     : in  std_logic;
      rst_clk_n : out std_logic
      );
  end component;
  component Enable_gen is
    port (clock_50    : in     std_logic;
          resetn      : in     std_logic;
          velg_enable : in     std_logic_vector(2 downto 0);
          enable      : buffer std_logic
          );
  end component;


begin
  LEDR(17)           <= hallo;
  clk                <= CLOCK_50;
  GPIO(5 downto 0)   <= state_output;
  LEDR(16 downto 13) <= GPIO(35 downto 32);
  reset_n            <= KEY(3);
  Velg_enable        <= SW(2 downto 0);
  -- Sensor2O, Sensor2V, Sensor1N, Sensor1S <= GPIO(35 downto 32);

  blink : Enable_gen
    port map(
      velg_enable => velg_enable,
      clock_50    => clk,
      resetn      => reset_n,
      enable      => Enable
      );

  blink_17 : process(clk)
  begin
    if rising_edge(clk) then
      if reset_n = '0' then
        hallo <= '0';
      elsif Enable = '1' then
        hallo <= not hallo;
      end if;
    end if;
  end process blink_17;

  tilstandsmaskin : process(clk)
  begin
    if rising_edge(clk) then
      if reset_n = '0' then
        state <= fase1;
      elsif Enable = '1' then
        teller <= teller + 1;
        case state is
          when fase1 =>
            if teller = fase_tid(0) then
              teller <= 0;
              state  <= fase2;
            end if;
          when fase2 =>
            if teller = fase_tid(1) then
              teller <= 0;
              state  <= fase3;
            end if;
          when fase3 =>
            if teller = fase_tid(2) then
              teller <= 0;
              state  <= fase4;
            end if;
          when fase4 =>
            if teller = fase_tid(3) then
              teller <= 0;
              state  <= fase5;
            end if;
          when fase5 =>
            if teller = fase_tid(4) then
              teller <= 0;
              state  <= fase6;
            end if;
          when fase6 =>
            if teller = fase_tid(5) then
              teller <= 0;
              state  <= fase1;
            end if;
          when others =>
            if teller = fase_tid(0) then
              teller <= 0;
              state  <= fase1;
            end if;
        end case;
      end if;
    end if;
  end process tilstandsmaskin;

  stae_values : process(state)
  begin
    case state is
      when fase1 =>
        state_output <= ROM_fase(0);
      when fase2 =>
        state_output <= ROM_fase(1);
      when fase3 =>
        state_output <= ROM_fase(2);
      when fase4 =>
        state_output <= ROM_fase(3);
      when fase5 =>
        state_output <= ROM_fase(4);
      when fase6 =>
        state_output <= ROM_fase(5);
      when others =>
        state_output <= ROM_fase(0);
    end case;
  end process;

end architecture RTL;