module binary_to_7segm
(
    input logic clk,
    input logic [15:0] binary_num,  // число на выход
    output logic [7:0]  segm,
    output logic [3:0]  dig

);
    logic[25:0] clockToSec = 0; // счет тактов
    logic [3:0] numb;
    logic [1:0] lcd_dig = 2'h0;

    always@(*)
    begin
        case (numb)
            //                   0gfedcba
            4'b0000 : segm <= 8'b00111111;
            4'b0001 : segm <= 8'b00000110;
            4'b0010 : segm <= 8'b01011011;
            4'b0011 : segm <= 8'b01001111;
            4'b0100 : segm <= 8'b01100110;
            4'b0101 : segm <= 8'b01101101;
            4'b0110 : segm <= 8'b01111101;
            4'b0111 : segm <= 8'b00000111;
            4'b1000 : segm <= 8'b01111111;
            4'b1001 : segm <= 8'b01101111;
            default : segm <= 8'b00111111;
        endcase
    end


    always @(posedge clk)           // по фронту
    begin
        //50 000
            clockToSec <= clockToSec + 1;       // счетчик + 1
            if(clockToSec == 26'hC350)      // если 50 000
            begin
                lcd_dig <= lcd_dig + 1;         // число на вывод + 1
                clockToSec <= 0;                    // обнуление счетчика
            end
        end

    always@(*)
    begin
        case (lcd_dig)
            2'b00 : begin
                    dig <= 4'b1110;
                    numb <= binary_num[3:0];
                end
            2'b01 : begin
                    dig <= 4'b1101;
                    numb <= binary_num[7:4];
                end
            2'b10 : begin
                    dig <= 4'b1011;
                    numb <= binary_num[11:8];
                end
            2'b11 : begin
                    dig <= 4'b0111;
                    numb <= binary_num[15:12];
                end
        endcase
    end

endmodule