rorod8

codigo practica7

Dec 4th, 2020
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use ieee.std_logic_unsigned.all;
  4.  
  5. use IEEE.NUMERIC_STD.ALL;
  6.  
  7.  
  8. entity pcunit is
  9.     Port ( clk_in : in STD_LOGIC;
  10.            pc_op_in : in STD_LOGIC_VECTOR (1 downto 0);
  11.            pc_in : in STD_LOGIC_VECTOR (15 downto 0);
  12.               AD : in STD_LOGIC_VECTOR(15 downto 0);
  13.              
  14.            pc_out : out STD_LOGIC_VECTOR (15 downto 0));
  15.              
  16. end pcunit;
  17.  
  18. architecture Behavioral of pcunit is
  19.     signal pc: STD_LOGIC_VECTOR(15 downto 0) := x"0000"; --set pc to 0000
  20. begin
  21.     process (clk_in)
  22.     begin
  23.         if rising_edge(clk_in) then
  24.             case pc_op_in is
  25.                 when "00" => -- increment
  26.                     pc <= STD_LOGIC_VECTOR(unsigned(pc) + 1);
  27.                 when "01" => -- branch
  28.                     pc <= pc + AD;
  29.                 when "10" => -- jump
  30.                     pc <= pc_in;
  31.                 when "11" => -- NOP
  32.                 when others =>
  33.             end case;
  34.         end if;
  35.     end process;
  36.    
  37.     pc_out <= pc;
  38.  
  39. end Behavioral;
  40.  
  41. library IEEE;
  42. use IEEE.STD_LOGIC_1164.ALL;
  43. use IEEE.STD_LOGIC_ARITH.ALL;
  44. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  45. entity extend is
  46. Port(
  47.     Instruction: in std_logic_vector (15 downto 0);
  48.     AD: out std_logic_vector (15 downto 0) 
  49.  
  50.     );
  51. end extend;
  52.  
  53. architecture comportamiento of extend is
  54. signal result: std_logic_vector (15 downto 0) := "0000000000000000"   ;
  55. begin   process(Instruction)
  56.     begin
  57.         if(Instruction(8)='0') then
  58.             result <= "0000000000" & Instruction(8 downto 6) & Instruction(2 downto 0);
  59.         else
  60.             result <= "1111111111" & Instruction(8 downto 6) & Instruction(2 downto 0);
  61.         end if;
  62.     end process;
  63.     AD<= result;
  64.  
  65. end comportamiento;
  66.  
  67. library IEEE;
  68. use IEEE.STD_LOGIC_1164.ALL;
  69. use IEEE.STD_LOGIC_ARITH.ALL;
  70. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  71. use ieee.NUMERIC_STD.all;
  72.  
  73. entity Instruction_Decoder is
  74. Port(
  75.     Instruction: in std_logic_vector (15 downto 0);
  76.     clk_in : in STD_LOGIC;
  77.     DA: out std_logic_vector(3 downto 0);
  78.     AA: out std_logic_vector(3 downto 0);
  79.     BA: out std_logic_vector(3 downto 0);
  80.    
  81.     MB: out std_logic;
  82.     FS: out std_logic_vector(3 downto 0);
  83.     MD: out std_logic;
  84.     RW: out std_logic;
  85.     MW: out std_logic;
  86.     PL: out std_logic;
  87.     JB: out std_logic;
  88.     BC: out std_logic
  89.    
  90.     );
  91. end Instruction_Decoder;
  92.  
  93. architecture comportamiento of Instruction_Decoder is
  94. begin
  95. process(clk_in)
  96.     begin
  97.         if rising_edge(clk_in) then
  98.           DA <= Instruction(8 downto 6);
  99.           AA <= Instruction(5 downto 3);
  100.           BA <= Instruction(2 downto 0);
  101.           MB <= Instruction(15);
  102.           FS <= Instruction(12 downto 10) & ((Instruction(9))and(not( Instruction(14) and Instruction(15) )));
  103.           MD <= Instruction(13);
  104.           RW <=  not (Instruction(14));
  105.           MW <= (Instruction(14)) and (not(Instruction(15)));
  106.           PL <= Instruction(14) and Instruction(15) ;
  107.           JB <= Instruction(13);
  108.           BC <= Instruction(9);
  109.  
  110.         end if;
  111. end process;
  112. end comportamiento;
  113.  
  114. library IEEE;
  115. use IEEE.STD_LOGIC_1164.ALL;
  116. use IEEE.STD_LOGIC_ARITH.ALL;
  117. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  118. entity Branch_control is
  119. Port(
  120.     PL : in STD_LOGIC;
  121.     JB : in STD_LOGIC;
  122.     BC : in STD_LOGIC;
  123.     N : in STD_LOGIC;
  124.     Z : in STD_LOGIC;
  125.     Y : out STD_LOGIC_VECTOR(1 DOWNTO 0)
  126.    
  127.     );
  128. end Branch_control;
  129.  
  130. architecture comportamiento of Branch_control is
  131. signal result: std_logic_vector (1 downto 0) := "00";
  132.  
  133. begin   process(PL,JB,BC,N,Z)
  134.     begin
  135.         if(PL='1') then
  136.             result <= "00";
  137.         else
  138.             if(JB='1') then
  139.                 result <="10";
  140.             else
  141.                 result <="01";
  142.             end if;
  143.         end if;
  144.        
  145.         if(BC = '1' and N = '1') then
  146.             result <="01";
  147.            
  148.         end if;
  149.        
  150.         if(BC = '0' and Z = '1') then
  151.             result <="01";
  152.            
  153.         end if;
  154.        
  155.     end process;
  156.     Y<= result;
  157.  
  158. end comportamiento;
  159.  
  160.  
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