mult_signed_reduced.v

module mult_signed_reduced(in1, in2, clk, out);
   input signed [3:0] in1;
   input signed [3:0] in2;
   output signed [3:0] out;
   input       clk;

   reg signed [8:0] pre_reduced_out;
   reg signed [3:0]   out;


   always @(posedge clk)
     begin
        pre_reduced_out = in1*in2;
        if (pre_reduced_out > 2**3)          out = 2**3-1;
        else if (pre_reduced_out < -2**3)          out = -2**3;
        else out = pre_reduced_out;
     end

endmodule