CPU REGISTERS
	Instruction Pointer (Program Counter)
	A Register (Accumulator)
	R Register (Data/Address Register)
	Z Register (Zero Flag Register)

	CPU INSTRUCTION SET REFERENCE

	Instruction    Addressing Mode    Operation Performed

	ADD address    Direct             A <- A + MEM(address)
	ADD A          Register           A <- A + A
	ADD R          Register           A <- A + R
	ADD M          Indirect           A <- A + MEM(R)
	ADD I, data    Immediate          A <- A + data

	CMP address    Direct             If A - MEM(address) = 0: Z <- 1
	CMP A          Register           If A - A = 0: Z <- 1
	CMP R          Register           If A - R = 0: Z <- 1
	CMP M          Indirect           If A - MEM(R) = 0: Z <- 1
	CMP I, data    Immediate          If A - data = 0: Z <- 1

	DEC address    Direct             A <- MEM(address) -1
	DEC A          Register           A <- A - 1
	DEC R          Register           A <- R - 1
	DEC M          Indirect           A <- MEM(R) - 1
	DEC I, data    Immediate          A <- data - 1

	IN address     Direct             A <- PORT(address)
	IN P           Indirect           A <- PORT(R)

	INV address    Direct             A <- [MEM(address)]’
	INV A          Register           A <- [A]’
	INV R          Register           A <- [R]’
	INV M          Indirect           A <- [MEM(R)]’
	INV I, data    Immediate          A <- [data]’

	JMP address    Direct             IP <- address
	JMP R          Register           IP <- R

	JNZ address    Direct             If Z = 0: JMP address
	JNZ R          Register           If Z = 0: JMP R

	JZ address     Direct             If Z = 1: JMP address
	JZ R           Register           If Z = 1: JMP R

	LDA address    Direct             A <- MEM(address)
	LDA A          Register           A <- A
	LDA R          Register           A <- R
	LDA M          Indirect           A <- MEM(R)
	LDA I, data    Immediate          A <- data

	LDR address    Direct             R <- MEM(address)
	LDR A          Register           R <- A
	LDR R          Register           R<- R
	LDR M          Indirect           R <- MEM(R)
	LDR I, data    Immediate          R <- data

	OR address     Direct             A <- A OR MEM(address)
	OR A           Register           A <- A OR A
	OR R           Register           A <- A OR R
	OR M           Indirect           A <- A OR MEM(R)
	OR I, data     Immediate          A <- A OR data

	OUT address    Direct             PORT(address) <- A
	OUT P          Indirect           PORT(R) <- A

	SHL address    Direct             A <- [MEM(address)]6..0 ## 0
	SHL A          Register           A <- [A]6..0 ## 0
	SHL R          Register           A <- [R]6..0 ## 0
	SHL M          Indirect           A <- [MEM(R)]6..0 ## 0
	SHL I, data    Immediate          A <- [data]6..0 ## 0

	STA address    Direct             MEM(address) <- A
	STA M          Indirect           MEM(R) <- A

	STR address    Direct             MEM(address) <- R
	STR M          Indirect           MEM(R) <- R

	SUB address    Direct             A <- A - MEM(address)
	SUB A          Register           A <- A - A
	SUB R          Register           A <- A - R
	SUB M          Indirect           A <- A - MEM(R)
	SUB I, data    Immediate          A <- A - data