module sample001_sum(KEY, LEDR, SW, HEX0, HEX1, HEX2, HEX3);
input [3:0] KEY;
input [9:0] SW;
output reg [9:0] LEDR;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
reg [9:0] H1;
reg [9:0] H2;
reg [9:0] H3;
reg [9:0] H4;


always
if (KEY[0] != 0 && KEY[1] != 0 && KEY[2] != 0 && KEY[3] != 0)
begin
    H1 = LEDR[9:5] % 10;
    H2 = (LEDR[9:5] / 10)% 10;
    H3 = LEDR[4:0]% 10;
    H4 = (LEDR[4:0] / 10)% 10;
end
else
begin
    H1 = (LEDR[9:0] / 100) % 10;
    H2 = (LEDR[9:0] / 1000)% 10;
    H3 = LEDR[9:0]% 10;
    H4 = (LEDR[9:0] / 10)% 10;
end

decToHex(H1, HEX2);
decToHex(
    (KEY[1] == 0) ?
        SW[9:5] < SW[4:0] ?
        H2
        : 11
    :H2
, HEX3);
decToHex(H3, HEX0);
decToHex(H4, HEX1);

always
if (KEY[0] == 0)
begin
    LEDR[9:0] = SW[9:5] + SW[4:0];
end
else if (KEY[1] == 0)
    if (SW[9:5] < SW[4:0])
        begin
            LEDR[9:0] = SW[4:0] - SW[9:5];
            // show minus here!
        end
    else
        LEDR[9:0] = SW[9:5] - SW[4:0];
else if (KEY[2] == 0)
    LEDR[9:0] = SW[9:5] * SW[4:0];
else
    LEDR[9:0] = SW[9:0];

endmodule


module decToHex(number, bits);

input [3:0] number;
output reg [6:0] bits;

always
case (number)
    0: bits = 7'b1000000;
    1: bits = 7'b1111001;
    2: bits = 7'b0100100;
    3: bits = 7'b0110000;
    4: bits = 7'b0011001;
    5: bits = 7'b0010010;
    6: bits = 7'b0000010;
    7: bits = 7'b1111000;
    8: bits = 7'b0000000;
    9: bits = 7'b0010000;
    11: bits = 7'b0111111;
    default: bits = 7'b1111111;
endcase
endmodule